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公开(公告)号：US20220277802A1
公开(公告)日：2022-09-01
申请号：US17747598
申请日：2022-05-18
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Chun Sum Yeung , Xiangang Luo
Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.
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公开(公告)号：US20220229728A1
公开(公告)日：2022-07-21
申请号：US17712978
申请日：2022-04-04
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung
IPC: G06F11/10 , G11C11/408 , G06F11/30 , G06F11/07
Abstract: A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.
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公开(公告)号：US20210391029A1
公开(公告)日：2021-12-16
申请号：US16903066
申请日：2020-06-16
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Chun Sum Yeung , Xiangang Luo
Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.
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公开(公告)号：US11106530B2
公开(公告)日：2021-08-31
申请号：US16723836
申请日：2019-12-20
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Falgun G. Trivedi , Harish Reddy Singidi , Xiangang Luo , Preston Allen Thomson , Ting Luo , Jianmin Huang
IPC: G06F11/10 , G06F12/02 , G06F12/0882 , G06F11/07
Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20240345947A1
公开(公告)日：2024-10-17
申请号：US18037631
申请日：2022-09-01
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Jianmin Huang , Xiaolai Zhu , Deping He , Kulachet Tanpairoj , Hong Lu , Chun Sum Yeung
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201 , G06F2212/7205
Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.
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Patent Agency Ranking
公开(公告)号：US20240282381A1
公开(公告)日：2024-08-22
申请号：US18426117
申请日：2024-01-29
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Kulachet Tanpairoj , Deping He
CPC classification number: G11C16/102 , G11C16/08
Abstract: Methods, systems, and devices for hybrid DWLSV are described. One or more controllers may communicate one or more program commands to a NAND memory device. The memory device may perform program operations that correspond to the program commands communicated by the controller. The memory device may perform the program operations using a word line start voltage. Once the programming operations are complete, the memory device may communicate the lowest word line starting voltage offset associated with performing the program operations to the one or more controllers.
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公开(公告)号：US20240256142A1
公开(公告)日：2024-08-01
申请号：US18420491
申请日：2024-01-23
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Pitamber Shukla , Zhongyuan Lu , Niccolo' Righetti
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/064 , G06F3/0679
Abstract: Methods, systems, and devices for managing partially programmed blocks are described. Based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. Based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.
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公开(公告)号：US11704196B2
公开(公告)日：2023-07-18
申请号：US17712978
申请日：2022-04-04
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung
IPC: G11C29/00 , G06F11/10 , G11C11/408 , G06F11/30 , G06F11/07
CPC classification number: G06F11/1076 , G06F11/0772 , G06F11/1068 , G06F11/3037 , G11C11/4085
Abstract: A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.
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公开(公告)号：US20230205450A1
公开(公告)日：2023-06-29
申请号：US18111213
申请日：2023-02-17
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Guang Hu , Ting Luo , Tao Liu
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.
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公开(公告)号：US20230024177A1
公开(公告)日：2023-01-26
申请号：US17959844
申请日：2022-10-04
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Deping He
IPC: G06F3/06
Abstract: A method includes receiving, by a processing device, signaling indicative of a power cycle (PC) to a memory device (MD) having a first signal indicative of a Power On Operation and a second signal indicative of a Power Off Operation, and determining an Average Power On Time (APOT) of the MD based, at least in part, on a quantity of power cycles (n) to the MD over a predetermined time interval (PTI), and for each PC over the PTI, an amount of time between receipt of the first signal and the second signal. A sum of each of the amount of time between receipt of the first signal and the second signal in the PTI provides a total power on time (T) to the MD, and the APOT is equal to T/n. When the APOT is less than (
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