公开(公告)号：US20150063826A1

公开(公告)日：2015-03-05

申请号：US14534635

申请日：2014-11-06

Applicant: Micron Technology, Inc.

Inventor： Roy Meade ,  Gurtej Sandhu

IPC: H04B10/516

CPC classification number: H04B10/516 ,  G02B6/12007 ,  G02B6/122 ,  G02B6/29343 ,  G02F1/035 ,  G02F1/2252

Abstract: An optical waveguide for transmitting an optical signal input to the optical waveguide with a first frequency. The optical waveguide includes a plurality of modulator circuits configured along an optical transmission channel. Each modulator circuit includes at least one resonant structure that resonates at the first frequency when the modulator circuit that includes the at least one resonant structure is at a resonant temperature. Each modulator circuit has a different resonant temperature.

Abstract translation: 一种光波导，用于以第一频率传输输入到光波导的光信号。 光波导包括沿着光传输通道配置的多个调制器电路。 每个调制器电路包括当包括至少一个谐振结构的调制器电路处于共振温度时以第一频率谐振的至少一个谐振结构。 每个调制器电路具有不同的谐振温度。

公开(公告)号：US20140341503A1

公开(公告)日：2014-11-20

申请号：US14446744

申请日：2014-07-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Roy Meade ,  Gurtej Sandhu

IPC: G02B6/122

CPC classification number: H01L21/76229 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/092 ,  H01L27/14689 ,  H01L29/0649

Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.

Abstract translation: 提供了一种形成具有适用于电子和光子器件集成的隔离区的衬底的方法。 常用的掩模版和光刻技术用于制造掩模，其限定用于蚀刻衬底中的第一和第二沟槽隔离区的开口，其中用于第二沟槽隔离区的开口比第一沟槽隔离区的开口宽。 通过掩模在衬底中蚀刻第一和第二沟槽隔离区域。 第二沟槽隔离区域被进一步蚀刻到比第一沟槽隔离区域更深的位置。 沟槽隔离区填充氧化物材料。 电子器件可以形成在衬底上并由第一沟槽隔离区域电隔离，并且光子器件可以形成在第二沟槽隔离区域上并且与衬底光学隔离。

公开(公告)号：US08815704B2

公开(公告)日：2014-08-26

申请号：US14151083

申请日：2014-01-09

Applicant: Micron Technology, Inc.

Inventor： Roy Meade ,  Gurtej Sandhu

IPC: H01L21/76 ,  H01L29/00

CPC classification number: H01L21/76229 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/092 ,  H01L27/14689 ,  H01L29/0649

Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.

Abstract translation: 提供了一种形成具有适用于电子和光子器件集成的隔离区的衬底的方法。 常用的掩模版和光刻技术用于制造掩模，其限定用于蚀刻衬底中的第一和第二沟槽隔离区的开口，其中用于第二沟槽隔离区的开口比第一沟槽隔离区的开口宽。 通过掩模在衬底中蚀刻第一和第二沟槽隔离区域。 第二沟槽隔离区域被进一步蚀刻到比第一沟槽隔离区域更深的位置。 沟槽隔离区填充氧化物材料。 电子器件可以形成在衬底上并由第一沟槽隔离区域电隔离，并且光子器件可以形成在第二沟槽隔离区域上并且与衬底光学隔离。

公开(公告)号：US20140153867A1

公开(公告)日：2014-06-05

申请号：US14176736

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu ,  Roy Meade

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1223 ,  G02B6/1225 ,  G02B6/13 ,  G02B2006/121 ,  H01L2933/0083

Abstract: A photonic device and methods of formation that provide an area providing reduced optical coupling between a substrate and an inner core of the photonic device are described. The area is formed using holes in the inner core and an outer cladding. The holes may be filled with materials which provide a photonic crystal. Thus, the photonic device may function as a waveguide and as a photonic crystal.

Abstract translation: 描述了提供在光子器件的衬底和内核之间提供减小的光学耦合的区域的光子器件和形成方法。 该区域由内芯和外包层中的孔形成。 孔可以填充提供光子晶体的材料。 因此，光子器件可以用作波导和光子晶体。

公开(公告)号：US20140097503A1

公开(公告)日：2014-04-10

申请号：US14105271

申请日：2013-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gurtej Sandhu

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/88

Abstract: A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.

Abstract translation: 一种存储器阵列，其包括各自电耦合到多于一个存储器单元的存取装置。 存储器单元通过二极管器件耦合到接入设备。 进入装置包括从形成第一和第二掺杂区域之间的导电通道的半导体基底直立的垂直半导体材料台面以及平面访问装置。

公开(公告)号：US08652934B1

公开(公告)日：2014-02-18

申请号：US13726891

申请日：2012-12-26

Applicant: Micron Technology, Inc.

Inventor： Roy Meade ,  Gurtej Sandhu

IPC: H01L21/76 ,  H01L29/00

CPC classification number: H01L21/76229 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/092 ,  H01L27/14689 ,  H01L29/0649

Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask and filled with an oxide material. The oxide material is removed from the bottom of the second trench isolation areas. The second trench isolation areas are further etched to the deeper than the first trench isolation areas, and are then filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.

Abstract translation: 提供了一种形成具有适用于电子和光子器件集成的隔离区的衬底的方法。 常用的掩模版和光刻技术用于制造限定用于蚀刻衬底中的第一和第二区域的开口的掩模，其中用于第二沟槽隔离区域的开口比第一沟槽隔离区域的开口宽。 通过掩模在衬底中蚀刻第一和第二沟槽隔离区域，并填充氧化物材料。 从第二沟槽隔离区域的底部去除氧化物材料。 第二沟槽隔离区进一步蚀刻到比第一沟槽隔离区更深的位置，然后用氧化物材料填充。 电子器件可以形成在衬底上并由第一沟槽隔离区域电隔离，并且光子器件可以形成在第二沟槽隔离区域上并且与衬底光学隔离。

公开(公告)号：US20140024141A1

公开(公告)日：2014-01-23

申请号：US14037064

申请日：2013-09-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: H01L29/66

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/66007 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract translation: 提供包括非磁性桥的磁性单元结构以及制造该结构的方法。 磁性电池结构包括自由层，钉扎层和电连接自由层和钉扎层的非磁性桥。 非磁性桥的形状和/或构造使编程电流通过磁性单元结构，使得结构自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

公开(公告)号：US20130286712A1

公开(公告)日：2013-10-31

申请号：US13930952

申请日：2013-06-28

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0002 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

Abstract: A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed.

Abstract translation: 公开了具有内置“on”状态整流IV特性的双极电流 - 电压（IV）电阻随机存取存储器单元的存储器阵列。 在一个实施例中，双极开关电阻随机存取存储器单元可以具有当切换到“导通”状态时形成肖特基二极管的金属/固体电解质/半导体堆叠。 在另一个实施例中，双极开关电阻随机存取存储器单元可以具有当切换到“导通”状态时形成金属 - 绝缘体 - 金属器件的金属/固体电解质/隧道势垒/电极堆叠。 还公开了操作存储器阵列的方法。

公开(公告)号：US20130102160A1

公开(公告)日：2013-04-25

申请号：US13710729

申请日：2012-12-11

Applicant: Micron Technology, Inc.

Inventor： Scott SIlls ,  Gurtej Sandhu ,  John Smythe ,  Ming Zhang

IPC: G03F7/20 ,  H01L21/027

CPC classification number: H01L21/0274 ,  G03F7/20 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338

Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

Abstract translation: 一些实施例包括形成开口图案的方法。 所述方法可以包括在衬底上形成间隔的特征。 特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。 第一材料可以沿着特征的顶部和侧壁形成。 第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。 在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。 然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

公开(公告)号：US11950514B2

公开(公告)日：2024-04-02

申请号：US17362322

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: H10N50/10 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.