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公开(公告)号：US09225322B2
公开(公告)日：2015-12-29
申请号：US14109341
申请日：2013-12-17
Applicant: Micron Technology, Inc.
CPC classification number: G06F1/06 , G06F1/08 , G06F1/324 , G06F1/3275 , H03K5/1515 , Y02D10/126 , Y02D10/14
Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.
Abstract translation: 本文描述了用于提供时钟信号的装置和方法。 示例性装置可以包括时钟发生器电路。 时钟发生器电路可以被配置为在时钟路径中选择性地向多路复用器提供第一和第二中间信号，以在第一模式下工作时提供具有第一频率的输出时钟信号，并且选择性地将第一和第二中间时钟信号提供给 时钟路径中的多路复用器，以在第二模式下操作时提供具有第二频率的输出时钟信号。
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公开(公告)号：US20210227986A1
公开(公告)日：2021-07-29
申请号：US17165533
申请日：2021-02-02
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri
Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
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公开(公告)号：US11074956B1
公开(公告)日：2021-07-27
申请号：US16806942
申请日：2020-03-02
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Ferdinando Bedeschi , Suryanarayana B. Tatapudi , Hyunyoo Lee , Adam S. El-Mansouri
IPC: G11C11/22
Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.
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公开(公告)号：US20200329881A1
公开(公告)日：2020-10-22
申请号：US16867420
申请日：2020-05-05
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri
Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
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公开(公告)号：US10755756B2
公开(公告)日：2020-08-25
申请号：US16508044
申请日：2019-07-10
Applicant: Micron Technology, Inc.
Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.
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Patent Agency Ranking
公开(公告)号：US10460777B2
公开(公告)日：2019-10-29
申请号：US16037546
申请日：2018-07-17
Applicant: Micron Technology, Inc.
Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.
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公开(公告)号：US10297294B2
公开(公告)日：2019-05-21
申请号：US15703365
申请日：2017-09-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis , Huy T. Vo , Dirgha Khatri
Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.
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公开(公告)号：US10026462B1
公开(公告)日：2018-07-17
申请号：US15596988
申请日：2017-05-16
Applicant: Micron Technology, Inc.
Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.
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公开(公告)号：US09570135B2
公开(公告)日：2017-02-14
申请号：US14174405
申请日：2014-02-06
Applicant: Micron Technology, Inc.
CPC classification number: G11C8/18 , G11C7/109 , G11C7/1093 , G11C7/222
Abstract: An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals.
Abstract translation: 示例延迟电路可以包括被配置为接收命令信号和/或库地址信号，第一时钟信号和第二时钟信号的延迟块，并且还被配置为向命令信号或存储体地址信号添加固有延迟 并且向第一和第二时钟信号添加大于本征延迟的前向路径延迟。
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公开(公告)号：US09471087B2
公开(公告)日：2016-10-18
申请号：US14958650
申请日：2015-12-03
Applicant: Micron Technology, Inc.
CPC classification number: G06F1/06 , G06F1/08 , G06F1/324 , G06F1/3275 , H03K5/1515 , Y02D10/126 , Y02D10/14
Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.
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