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    Memory Cells and Methods of Forming Memory Cells
    13.
    发明申请
    Memory Cells and Methods of Forming Memory Cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US20140158965A1

    公开(公告)日：2014-06-12

    申请号：US14182491

    申请日：2014-02-18

    Applicant: Micron Technology, Inc.

    Inventor： John Smythe ,  Gurtej S. Sandhu

    IPC: H01L45/00

    CPC classification number: H01L45/12 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L45/1675

    Abstract: A method of forming a memory cell includes forming programmable material within an opening in dielectric material over an elevationally inner conductive electrode of the memory cell. Conductive electrode material is formed over the dielectric material and within the opening. The programmable material within the opening has an elevationally outer edge surface angling elevationally and laterally inward relative to a sidewall of the opening. The conductive electrode material is formed to cover over the angling surface of the programmable material within the opening. The conductive electrode material is removed back at least to an elevationally outermost surface of the dielectric material and to leave the conductive electrode material covering over the angling surface of the programmable material within the opening. The conductive electrode material constitutes at least part of an elevationally outer conductive electrode of the memory cell. Memory cells independent of method of manufacture are also disclosed.

    Abstract translation: 形成存储单元的方法包括在电介质材料的开口内形成可编程材料，该存储单元在存储单元的顶部内导电电极之上。 导电电极材料形成在电介质材料上并且在开口内。 开口内的可编程材料具有相对于开口的侧壁正向和横向向内倾斜的垂直外边缘表面。 导电电极材料形成为覆盖开口内可编程材料的倾斜表面。 导电电极材料至少移除到介电材料的最外表面，并将导电电极材料覆盖在开口内的可编程材料的倾斜表面上。 导电电极材料构成存储单元的正面外导电电极的至少一部分。 还公开了与制造方法无关的存储单元。

    SEMICONDUCTOR MATERIAL MANUFACTURE
    14.
    发明申请
    SEMICONDUCTOR MATERIAL MANUFACTURE 审中-公开
    半导体材料制造

    公开(公告)号：US20130175662A1

    公开(公告)日：2013-07-11

    申请号：US13784431

    申请日：2013-03-04

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha ,  Gurtej S. Sandhu ,  John Smythe

    IPC: H01L21/762

    CPC classification number: H01L21/76254

    Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 电子设备，系统和方法包括结合到晶片或基板的主体区域的半导体层，其中半导体层可以使用电磁辐射结合到主体区域。 公开了附加装置，系统和方法。

    Methods of Forming Patterns
    15.
    发明申请
    Methods of Forming Patterns 有权
    形成模式的方法

    公开(公告)号：US20130102160A1

    公开(公告)日：2013-04-25

    申请号：US13710729

    申请日：2012-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Scott SIlls ,  Gurtej Sandhu ,  John Smythe ,  Ming Zhang

    IPC: G03F7/20 ,  H01L21/027

    CPC classification number: H01L21/0274 ,  G03F7/20 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338

    Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

    Abstract translation: 一些实施例包括形成开口图案的方法。 所述方法可以包括在衬底上形成间隔的特征。 特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。 第一材料可以沿着特征的顶部和侧壁形成。 第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。 在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。 然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

    Methods of Forming a Non-Volatile Resistive Oxide Memory Cell and Methods of Forming a Non-Volatile Resistive Oxide Memory Array
    17.
    发明申请
    Methods of Forming a Non-Volatile Resistive Oxide Memory Cell and Methods of Forming a Non-Volatile Resistive Oxide Memory Array 有权
    形成非易失性电阻氧化物记忆单元的方法和形成非易失性电阻氧化物存储器阵列的方法

    公开(公告)号：US20160260899A1

    公开(公告)日：2016-09-08

    申请号：US15156105

    申请日：2016-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

    Abstract translation: 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。

    Capacitors Having Dielectric Regions that Include Multiple Metal Oxide-Comprising Materials
    18.
    发明申请
    Capacitors Having Dielectric Regions that Include Multiple Metal Oxide-Comprising Materials 审中-公开
    具有包含多种金属氧化物的材料的介电区域的电容器

    公开(公告)号：US20150001674A1

    公开(公告)日：2015-01-01

    申请号：US14486075

    申请日：2014-09-15

    Applicant: Micron Technology, Inc.

    Inventor： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hull ,  Chris Carlson

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/56 ,  H01G4/10 ,  H01L27/108

    Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.

    Abstract translation: 公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。 电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。 公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / cm 2 + 1.1V。

    Memory Cells and Memory Cell Arrays
    19.
    发明申请
    Memory Cells and Memory Cell Arrays 有权
    存储单元和存储单元阵列

    公开(公告)号：US20140339494A1

    公开(公告)日：2014-11-20

    申请号：US14448352

    申请日：2014-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

    Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

    Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

    Methods of self-aligned growth of chalcogenide memory access device
    20.
    发明授权
    Methods of self-aligned growth of chalcogenide memory access device 有权
    硫属化物存储器存取装置的自对准生长方法

    公开(公告)号：US08853682B2

    公开(公告)日：2014-10-07

    申请号：US14185094

    申请日：2014-02-20

    Applicant: Micron Technology, Inc.

    Inventor： Neil Greeley ,  Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

    IPC: H01L29/06 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

    Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

    Abstract translation: 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

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