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公开(公告)号：US11361825B2
公开(公告)日：2022-06-14
申请号：US16719745
申请日：2019-12-18
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Michael Sheperek , Larry J. Koudele
Abstract: A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.
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公开(公告)号：US20220091935A1
公开(公告)日：2022-03-24
申请号：US17544772
申请日：2021-12-07
Applicant: Micron Technology, Inc.
Inventor： Mustafa N. Kaynak , Larry J. Koudele , Michael Sheperek , Patrick R. Khayat , Sampath K. Ratnam
Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.
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公开(公告)号：US20220076765A1
公开(公告)日：2022-03-10
申请号：US17014583
申请日：2020-09-08
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Larry J. Koudele
Abstract: An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.
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公开(公告)号：US11270772B1
公开(公告)日：2022-03-08
申请号：US17008225
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Michael Sheperek , Larry J. Koudele , Shane Nowell
Abstract: One or more blocks at the memory device are programed. The one or more blocks are associated with a block family and with one or more dice of a die group. A voltage offset bin associated with the die group and the block family is determined based on a subset of dice of the die group. Metadata associated with the memory device is appended to include a record associating the die group and the block family with the voltage offset bin.
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公开(公告)号：US11263134B1
公开(公告)日：2022-03-01
申请号：US17008024
申请日：2020-08-31
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Larry J. Koudele , Mustafa N. Kaynak , Shane Nowell
IPC: G06F12/0802 , G06F12/06 , G11C16/10
Abstract: A set of two or more block families associated with a first voltage bin are selected. Each block family includes two or more pages of a memory device that have been programmed within a corresponding time window. The set of two or more block families includes a first block family and a second block family. Values of a data state metric for each of the set of block families is determined. A first voltage for the first block family and a second voltage for the second block family is determined based on the values of the data state metric. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.
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Patent Agency Ranking
公开(公告)号：US11200956B2
公开(公告)日：2021-12-14
申请号：US16856587
申请日：2020-04-23
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Bruce A. Liikanen , Michael Sheperek
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.
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公开(公告)号：US20210335428A1
公开(公告)日：2021-10-28
申请号：US16856587
申请日：2020-04-23
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Bruce A. Liikanen , Michael Sheperek
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.
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公开(公告)号：US10748625B1
公开(公告)日：2020-08-18
申请号：US16295857
申请日：2019-03-07
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Bruce A. Liikanen
Abstract: A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.
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公开(公告)号：US20200133510A1
公开(公告)日：2020-04-30
申请号：US16170423
申请日：2018-10-25
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Bruce A. Liikanen , Steve Kientz
IPC: G06F3/06
Abstract: A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.
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公开(公告)号：US20200075111A1
公开(公告)日：2020-03-05
申请号：US16122410
申请日：2018-09-05
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Bruce A. Liikanen
Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a DPT operation on the memory cell to calibrate a first program-verify (PV) target corresponding to a first first-pass programming distribution and a second PV target corresponding to a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.
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