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公开(公告)号：US12119062B2
公开(公告)日：2024-10-15
申请号：US17884113
申请日：2022-08-09
CPC分类号： G11C16/08 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/10 , G11C16/3459 , G11C16/0483
摘要： Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.
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2.发明公开公开(公告)号：US20240338146A1
公开(公告)日：2024-10-10
申请号：US18743629
申请日：2024-06-14
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.
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公开(公告)号：US20240256328A1
公开(公告)日：2024-08-01
申请号：US18419352
申请日：2024-01-22
IPC分类号： G06F9/48
CPC分类号： G06F9/485
摘要： Methods, systems, and apparatuses mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and current bit is selected. In response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion, it is determined that the current bit was flipped in a previous iteration. The flipping of the current bit is bypassed in response to determining the current bit was flipped in the previous iteration.
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4.发明授权公开(公告)号：US11996860B2
公开(公告)日：2024-05-28
申请号：US17829924
申请日：2022-06-01
CPC分类号： H03M13/1108 , H03M13/1128 , H03M13/1148 , H03M13/6511
摘要： A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.
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公开(公告)号：US20230325273A1
公开(公告)日：2023-10-12
申请号：US18207525
申请日：2023-06-08
发明人： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0751 , G06F11/0727
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.
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公开(公告)号：US11783901B2
公开(公告)日：2023-10-10
申请号：US17880980
申请日：2022-08-04
发明人： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Karl D. Schuh , Jiangang Wu , Devin M. Batutis , Xiangang Luo
CPC分类号： G11C16/34 , G06F3/0604 , G06F3/0632 , G06F3/0659 , G06F3/0679 , G06F11/076 , G06F11/0727 , G06F11/0793 , G11C16/26 , G11C16/0483
摘要： A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.
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公开(公告)号：US20230308114A1
公开(公告)日：2023-09-28
申请号：US17706471
申请日：2022-03-28
CPC分类号： H03M13/1108 , H03M13/611
摘要： Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Syndrome information and energy function values are determined for bits of the codeword. A bit flipping criterion is selected using the syndrome information from a plurality of values. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies the bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.
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公开(公告)号：US11748013B2
公开(公告)日：2023-09-05
申请号：US17949977
申请日：2022-09-21
发明人： Kishore Kumar Muchherla , Mustafa N. Kaynak , Jiangang Wu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Peter Feeley , Karl D. Schuh
CPC分类号： G06F3/064 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G11C16/10 , G11C16/0483
摘要： An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.
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公开(公告)号：US11676664B2
公开(公告)日：2023-06-13
申请号：US17883538
申请日：2022-08-08
发明人： Kishore Kumar Muchherla , Sampath K. Ratnam , Shane Nowell , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Karl D. Schuh , Peter Feeley , Jiangang Wu
CPC分类号： G11C16/102 , G11C16/20 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3495
摘要： A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.
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公开(公告)号：US20230122275A1
公开(公告)日：2023-04-20
申请号：US18083992
申请日：2022-12-19
发明人： Kishore Kumar Muchherla , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Xiangang Luo , Peter Feeley , Devin M. Batutis , Jiangang Wu , Sampath K. Ratnam , Shane Nowell , Karl D. Schuh
摘要： A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.
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