公开(公告)号：US20020083401A1

公开(公告)日：2002-06-27

申请号：US09932064

申请日：2001-08-17

Applicant: Micron Technology, Inc.

Inventor： Lyle Breiner ,  Randhir P.S. Thakur

IPC: G06F017/50

CPC classification number: G03F7/70625 ,  H01L22/20

Abstract: This invention pertains to a method for the systematic development of integrated chip technology. The method may include obtaining empirical data of parameters for an existing integrated circuit manufacturing process and extrapolating the known data to a new technology to assess potential yields of the new technology from the known process. Further, process variables of the new process may be adjusted based upon the empirical data in order to optimize the yields of the new technology. A logic based computing system such as a fuzzy logic or neural-network system may be utilized. The computing system may also be utilized to improve the yields of an existing manufacturing process by adjust process variables within downstream process tools based upon data collected in upstream process for a particular semiconductor substrate or lot.

Abstract translation: 本发明涉及集成芯片技术的系统开发的方法。 该方法可以包括获得用于现有集成电路制造过程的参数的经验数据，并将已知数据外插到新技术，以从已知过程评估新技术的潜在产量。 此外，可以基于经验数据来调整新过程的过程变量，以便优化新技术的收益率。 可以使用诸如模糊逻辑或神经网络系统的基于逻辑的计算系统。 还可以使用计算系统来通过基于在特定半导体衬底或批次的上游工艺中收集的数据来调整下游工艺工具内的工艺变量来提高现有制造工艺的产量。

公开(公告)号：US20010016417A1

公开(公告)日：2001-08-23

申请号：US09761355

申请日：2001-01-16

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur ,  John K. Zahurak

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76856 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76882 ,  Y10S438/909

Abstract: According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized. According to another embodiment of the invention, a conductive plug fill material is deposited within a contact hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill, at a pressure of at least approximately 1.1 atmospheres. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized for the force-fill. Aluminum can be used for the conductive plug fill material when using this embodiment of the invention. In further embodiments, dielectrics deposited between conductive layers are reflowed at high pressure and low temperature. Still further, multiple metalized layers are connected by vias filled with conductive material using high pressure and low temperature.

Abstract translation: 根据本发明的一个实施例，利用高压退火在接触孔的底部，在沉积的钛和下面的硅之间的反应压力至少约1.1个大气压下形成硅化钛。 当使用这样的高压时，使用小于约700摄氏度的温度。 根据本发明的另一个实施例，导电插塞填充材料沉积在接触孔内，使得插塞结构相对没有空隙。 在沉积导电插塞填充材料期间或在这种沉积之后，导电插塞填充材料在至少约1.1个大气压的压力下经受高压力填充。 当使用这种高压时，小于约700摄氏度的温度被用于强制填充。 当使用本发明的该实施例时，铝可用于导电塞填充材料。 在另外的实施例中，沉积在导电层之间的电介质在高压和低温下回流。 此外，多个金属化层通过使用高压和低温填充导电材料的通孔连接。

公开(公告)号：US20030030093A1

公开(公告)日：2003-02-13

申请号：US10223805

申请日：2002-08-19

Applicant: Micron Technology, Inc.

Inventor： Vishnu K. Agarwal ,  F. Daniel Gealy ,  Kunal R. Parekh ,  Randhir P.S. Thakur

IPC: H01L021/8242 ,  H01L027/108 ,  H01L029/94 ,  H01L031/119

CPC classification number: H01L28/40 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5222 ,  H01L28/57 ,  H01L28/84 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least within the opening. Threshold voltage inducing material can be provided over the barrier layer but be retarded in movement into an electronic device comprised by the substrate. The dielectric layer can comprise a tantalum oxide and the barrier layer can include a silicon nitride. Providing threshold voltage shift inducing material can include oxide annealing dielectric layer such as with N2O. The barrier layer can be formed over the insulation layer, the insulation layer can be formed over the barrier layer, or the barrier layer can be formed over a first insulation layer with a second insulation layer formed over the barrier layer. Further, the barrier layer can be formed after forming the capacitor electrode or after forming the dielectric layer, for example, by using poor step coverage deposition methods.

公开(公告)号：US20030015769A1

公开(公告)日：2003-01-23

申请号：US10232205

申请日：2002-08-29

Applicant: Micron Technology, Inc.

Inventor： Scott Jeffrey DeBoer ,  Husam N. Al-Shareef ,  Randhir P.S. Thakur ,  Dan Gealy

IPC: H01L029/00

CPC classification number: H01L21/02326 ,  G11C17/16 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/31637 ,  H01L23/5252 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/112 ,  H01L27/11206 ,  H01L28/40 ,  H01L28/65 ,  H01L28/84 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.