公开(公告)号：US20180138033A1

公开(公告)日：2018-05-17

申请号：US15867993

申请日：2018-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Brian Dolan ,  Robert J. Hanson ,  Chan Lim

IPC: H01L21/02 ,  H01L21/66

CPC classification number: H01L21/02071 ,  H01L22/12 ,  H01L22/20

Abstract: Methods of removing metal from a portion of a substrate include exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent, determining whether metal remaining on the portion of the substrate is less than or equal to a particular level, and exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent if the metal remaining on the portion of the substrate is deemed to be greater than the particular level.

公开(公告)号：US09887077B2

公开(公告)日：2018-02-06

申请号：US15070456

申请日：2016-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Brian Dolan ,  Robert J. Hanson ,  Chan Lim

IPC: B08B3/00 ,  H01L21/02 ,  H01L21/66

CPC classification number: H01L21/02071 ,  H01L22/12 ,  H01L22/20

Abstract: Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, determining whether metal remaining on the portion of the substrate is less than or equal to a particular level, and if the metal remaining on the portion of the substrate is deemed to be greater than the particular level, exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent.

公开(公告)号：US20160196967A1

公开(公告)日：2016-07-07

申请号：US15070456

申请日：2016-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Brian Dolan ,  Robert J. Hanson ,  Chan Lim

IPC: H01L21/02 ,  H01L21/66

CPC classification number: H01L21/02071 ,  H01L22/12 ,  H01L22/20

Abstract: Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, determining whether metal remaining on the portion of the substrate is less than or equal to a particular level, and if the metal remaining on the portion of the substrate is deemed to be greater than the particular level, exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent.

Abstract translation: 从基板的一部分去除金属的方法在集成电路制造中是有用的。 方法包括将衬底暴露于包含至少一种氧化剂和至少一种还原剂的氧化环境中，确定残留在衬底部分上的金属是否小于或等于特定水平，并且如果残留在该部分上的金属 被认为大于特定水平，将底物暴露于包含至少一种还原剂和至少一种氧化剂的还原环境中。

公开(公告)号：US08969217B2

公开(公告)日：2015-03-03

申请号：US13948043

申请日：2013-07-22

Applicant: Micron Technology, Inc.

Inventor： Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  B08B3/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/02052 ,  H01L21/31111

Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

Abstract translation: 一些实施方案包括处理半导体衬底的方法。 衬底可以暴露于连续变化的一个或多个条件。 条件可以包括温度梯度，一种或多种淬灭蚀刻剂的组合物的浓度梯度，有助于除去颗粒的pH梯度和/或一种或多种有助于除去颗粒的组合物的浓度梯度。 可以通过将半导体衬底放置在流动的漂洗溶液浴中来赋予连续变化的条件，浴中具有至少两条在其中提供漂洗溶液的进料管线。 供给管线中的一个可以处于第一状态，另一个可以处于与第一条件不同的第二条件。 可以改变通过每个进料管提供给浴的冲洗溶液的相对量，以连续地改变浴内的状态。

公开(公告)号：US20150054164A1

公开(公告)日：2015-02-26

申请号：US13975722

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Gowrisankar Damarla ,  Robert J. Hanson ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

Abstract translation: 一些实施例包括具有在交叉点处彼此相交的第一和第二导电线的半导体结构。 第一线主要具有第一宽度，并且具有直接相对于第二线并且在第二线的相对侧彼此变窄的区域。 导电触头沿着第一线并且直接电耦合到第一线，并且一个导电触头直接抵靠该交叉。 一些实施例包括形成相交线材料的方法。 形成第一和第二沟槽，并在相交处相互交叉。 第一沟槽主要具有第一宽度，并且将区域直接靠在第二沟槽和第二沟槽的相对侧上彼此变窄。 材料沉积在第一和第二沟槽内，以基本上完​​全填充第一和第二沟槽。

公开(公告)号：US20130230957A1

公开(公告)日：2013-09-05

申请号：US13865117

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Robert J. Hanson ,  Sanh D. Tang

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7834

Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括形成场效应晶体管的方法。 在一个实施方案中，本发明包括在衬底上形成场效应晶体管的方法，其中场效应晶体管包括一对导电掺杂的源极/漏极区域，在该对源极/漏极区域之间接收的沟道区域，以及 晶体管栅极可靠地接收在沟道区域。 这种实现包括在沉积材料之前对该对源极/漏极区进行掺杂剂激活退火，从而制造晶体管栅极的导电部分。 考虑了其他方面和实现。