公开(公告)号：US20250142875A1

公开(公告)日：2025-05-01

申请号：US19011229

申请日：2025-01-06

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Hong Li ,  Erica L. Poelstra

IPC: H10D30/63 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L23/49 ,  H01L23/528 ,  H10B12/00 ,  H10B63/00 ,  H10D30/01 ,  H10D62/10 ,  H10D62/17 ,  H10D84/01 ,  H10D84/03

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

公开(公告)号：US12150292B2

公开(公告)日：2024-11-19

申请号：US17891480

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H10B12/00

Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11864386B2

公开(公告)日：2024-01-02

申请号：US17837879

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

IPC: H10B43/27 ,  H10B51/00 ,  H10B53/20 ,  G06F3/06

CPC classification number: H10B43/27 ,  G06F3/0688 ,  H10B51/00 ,  H10B53/20

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

公开(公告)号：US20230413559A1

公开(公告)日：2023-12-21

申请号：US18209173

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  john K. Zahurak

IPC: H10B43/27 ,  H01L21/28 ,  H01L27/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H10B63/00 ,  H01L21/768 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528

CPC classification number: H10B43/27 ,  H10N70/231 ,  H01L27/0688 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H10B63/34 ,  H10B63/845 ,  H01L21/76838 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L29/40114

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US11706909B2

公开(公告)日：2023-07-18

申请号：US17083174

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mitsunari Sukekawa ,  Yusuke Yamamoto ,  Christopher J. Kawamura ,  Hiroaki Taketani

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/31 ,  H01L23/5283 ,  H10B12/033 ,  H10B12/05 ,  H10B12/488

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230171962A1

公开(公告)日：2023-06-01

申请号：US18096341

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L28/00 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11569266B2

公开(公告)日：2023-01-31

申请号：US17308766

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20220406785A1

公开(公告)日：2022-12-22

申请号：US17891480

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11177266B2

公开(公告)日：2021-11-16

申请号：US16550917

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kirk D. Prall ,  Mitsunari Sukekawa

IPC: H01L27/108

Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

公开(公告)号：US20210351087A1

公开(公告)日：2021-11-11

申请号：US16868133

申请日：2020-05-06

Applicant: Micron Technology, Inc.

Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Yunfei Gao ,  Sanh D. Tang ,  Haitao Liu

IPC: H01L21/84 ,  H01L21/265

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.