公开(公告)号：US12039163B2

公开(公告)日：2024-07-16

申请号：US17822250

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Scheheresade Virani ,  Jeffrey Lee Munsil

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679

Abstract: Implementations described herein relate to memory device log data storage. In some implementations, a memory device may store a first data stream associated with a first type of log data in a circular buffer. The memory device may store a second data stream associated with a second type of log data in another memory location. The memory device may detect an event included in the second data stream that is associated with an attribute level that satisfies a threshold. The memory device may write data stored in the circular buffer after a time at which the event is detected to a non-volatile memory based on the attribute level satisfying the threshold, wherein the data stored in the circular buffer is stored in the non-volatile memory in connection with data associated with the event.

公开(公告)号：US12001717B2

公开(公告)日：2024-06-04

申请号：US17822895

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Scheheresade Virani

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: Implementations described herein relate to memory device operations for unaligned write operations. In some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. The memory device may allocate a set of buffers for the write command. The memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. The memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. The memory device may write the data unit to memory indicated by the set of physical addresses.

公开(公告)号：US11962500B2

公开(公告)日：2024-04-16

申请号：US17898018

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Aleksei Vlasov ,  Prateek Sharma ,  Yoav Weinberg ,  Scheheresade Virani ,  Bridget L. Mallak

IPC: H04L45/74 ,  H04L45/30

CPC classification number: H04L45/74 ,  H04L45/30

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

公开(公告)号：US20220417149A1

公开(公告)日：2022-12-29

申请号：US17898018

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Aleksei Vlasov ,  Prateek Sharma ,  Yoav Weinberg ,  Scheheresade Virani ,  Bridget L. Mallak

IPC: H04L45/74 ,  H04L45/30

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

公开(公告)号：US11385820B2

公开(公告)日：2022-07-12

申请号：US16809360

申请日：2020-03-04

Applicant: Micron Technology, Inc.

Inventor： John Paul Traver ,  Yun Li ,  Scheheresade Virani ,  Ning Zhao ,  Tom Victor Maria Geukens

IPC: G06F3/06

Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

公开(公告)号：US11042481B1

公开(公告)日：2021-06-22

申请号：US16720674

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Scheheresade Virani ,  Byron D. Harris

IPC: G06F12/00 ,  G06F12/0873 ,  G06F12/02 ,  G06F9/54 ,  G06F9/30 ,  G06F9/50 ,  G06F12/10

Abstract: A read command is received from a host system, which operates on a first logical block address (LBA) range that at least partially overlaps with a second LBA range associated with a write command. A state associated with the write command is determined, where the state is indicative of whether a logical-to-physical (L2P) mapping table has been updated based on the write command. Data corresponding to the first LBA range is transmitted to the host system based on the state associated with the write command.

公开(公告)号：US20240311288A1

公开(公告)日：2024-09-19

申请号：US18591692

申请日：2024-02-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle Brock-Petersen ,  Scheheresade Virani ,  Steven Gaskill

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Described are systems and methods for internal log management in memory sub-systems. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: maintaining a write pointer referencing a next data item position within a log buffer residing on a memory device of the one or more memory devices; maintaining a log retrieval pointer referencing a data retrieval position within the log buffer; storing, at a log buffer position specified by the write pointer, a data item reflecting a state of the system; advancing the write pointer by a size of the data item; responsive to determining that the write pointer exceeds an end of the log buffer, wrapping the write pointer around the end of the log buffer; responsive to receiving, from a host, a log retrieval request, retrieving the log data starting from the position within the log buffer referenced by the log retrieval pointer; transmitting the retrieved log data to the host; advancing the log retrieval pointer by a size of the retrieved log data; responsive to determining that the log retrieval pointer exceeds the end of the log buffer, wrapping the log retrieval pointer around the end of the log buffer.

公开(公告)号：US11755227B2

公开(公告)日：2023-09-12

申请号：US17860999

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： John Paul Traver ,  Yun Li ,  Scheheresade Virani ,  Ning Zhao ,  Tom Victor Maria Geukens

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

公开(公告)号：US11630778B2

公开(公告)日：2023-04-18

申请号：US17322522

申请日：2021-05-17

Applicant: Micron Technology, Inc.

Inventor： Scheheresade Virani ,  Byron D. Harris

IPC: G06F12/00 ,  G06F12/0873 ,  G06F9/50 ,  G06F9/54 ,  G06F12/02 ,  G06F9/30 ,  G06F12/10

Abstract: A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.

公开(公告)号：US11579799B2

公开(公告)日：2023-02-14

申请号：US16822916

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Mark Ish ,  Yun Li ,  Scheheresade Virani ,  John Paul Traver ,  Ning Zhao

IPC: G06F3/06 ,  G06F9/50

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.