公开(公告)号：US20240264743A1

公开(公告)日：2024-08-08

申请号：US18636783

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Brian Toronyi ,  Scheheresade Virani

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

公开(公告)号：US20230161509A1

公开(公告)日：2023-05-25

申请号：US18099504

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Mark Ish ,  Yun Li ,  Scheheresade Virani ,  John Paul Traver ,  Ning Zhao

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0659 ,  G06F9/5027 ,  G06F3/0673 ,  G06F3/0604

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

公开(公告)号：US12001678B2

公开(公告)日：2024-06-04

申请号：US17895696

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Brian Toronyi ,  Scheheresade Virani

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

公开(公告)号：US20210303470A1

公开(公告)日：2021-09-30

申请号：US16833306

申请日：2020-03-27

Applicant: Micron Technology, Inc.

Inventor： Scheheresade Virani ,  Aleksei Vlasov ,  Mark Ish

IPC: G06F12/0853 ,  G06F12/123 ,  G06F9/50 ,  G06F11/30

Abstract: Methods, systems, and devices for sequential prefetching through a linking array are described. A prefetch manager can detect that a set of tags occupying a queue of a memory sub-system corresponds to a single read descriptor indicating a sequential read pattern. The prefetch manager can determine that a number of the set of tags occupying the queue is below a queue threshold and store data associated with at least one tag of the set of tags in an internal performance memory of the memory sub-system based on the detecting and the determining. In such cases, the prefetch manager can prefetch data from a memory manager and store in the internal performance memory.

公开(公告)号：US12182447B2

公开(公告)日：2024-12-31

申请号：US18099504

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Mark Ish ,  Yun Li ,  Scheheresade Virani ,  John Paul Traver ,  Ning Zhao

IPC: G06F9/50 ,  G06F3/06

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

公开(公告)号：US20240069728A1

公开(公告)日：2024-02-29

申请号：US17895696

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Brian Toronyi ,  Scheheresade Virani

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/1009

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

公开(公告)号：US11431629B2

公开(公告)日：2022-08-30

申请号：US16991376

申请日：2020-08-12

Applicant: Micron Technology, Inc.

Inventor： Aleksei Vlasov ,  Prateek Sharma ,  Yoav Weinberg ,  Scheheresade Virani ,  Bridget L. Mallak

IPC: H04L45/74 ,  H04L45/30

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

公开(公告)号：US20210294522A1

公开(公告)日：2021-09-23

申请号：US16822916

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Mark Ish ,  Yun Li ,  Scheheresade Virani ,  John Paul Traver ,  Ning Zhao

IPC: G06F3/06 ,  G06F9/50

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

公开(公告)号：US20210191870A1

公开(公告)日：2021-06-24

申请号：US16720674

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Scheheresade Virani ,  Byron D. Harris

IPC: G06F12/0873 ,  G06F9/50 ,  G06F9/54 ,  G06F12/02 ,  G06F9/30

Abstract: A read command is received from a host system, which operates on a first logical block address (LBA) range that at least partially overlaps with a second LBA range associated with a write command. A state associated with the write command is determined, where the state is indicative of whether a logical-to-physical (L2P) mapping table has been updated based on the write command. Data corresponding to the first LBA range is transmitted to the host system based on the state associated with the write command.

公开(公告)号：US20210191652A1

公开(公告)日：2021-06-24

申请号：US16726124

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Ning Zhao ,  Yun Li ,  Scheheresade Virani ,  Zachary Andrew Pete Vogel

IPC: G06F3/06

Abstract: Methods, systems, and devices for linking access commands for a memory sub-system of a memory sub-system are described. A first write command that includes first data can be received. The first write command can be associated with a first identifier. An internal read command to retrieve data stored in the transfer unit of the memory sub-system can be issued based on receiving the first write command. A second write command that includes second data can be received. The second write command can be associated with a second identifier. The first and second identifiers can be linked based on receiving the second write command and an internal write command that includes the first data associated with the first write command and the second data associated with the second write command can be issued.