公开(公告)号：US20140286092A1

公开(公告)日：2014-09-25

申请号：US14227295

申请日：2014-03-27

Applicant: Micron Technology, Inc.

Inventor： Uday Chandrasekhar ,  Mark A. Helm

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454

Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

Abstract translation: 本公开涉及内存扭结检查。 一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。 至少部分地由于施加到第一数据线的电压和至少第一数据线与第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到 第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。 响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。

公开(公告)号：US08806155B2

公开(公告)日：2014-08-12

申请号：US13775645

申请日：2013-02-25

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Uday Chandrasekhar ,  Dean Nobunaga

IPC: G06F13/00 ,  G06F3/06 ,  G06F12/08 ,  G06F13/10

CPC classification number: G06F3/0601 ,  G06F3/0628 ,  G06F3/0653 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F13/102 ,  G06F2212/214 ,  G06F2212/313 ,  Y02D10/13

Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.

Abstract translation: 存储器设备和方法通过使用数据分组和将数据有效性状态值分配给分组数据来促进对由存储器设备接收的数据的处理。 例如，数据被接收并被描绘成一个或多个数据组，并且数据有效性状态与每个数据组相关联。 具有有效状态的数据组被锁存到一个或多个高速缓存寄存器中以存储在存储器单元阵列中，其中包括无效状态的数据组被一个或多个高速缓存寄存器拒绝。

公开(公告)号：US08804419B2

公开(公告)日：2014-08-12

申请号：US13938078

申请日：2013-07-09

Applicant: Micron Technology, Inc.

Inventor： Uday Chandrasekhar ,  Mark A. Helm

IPC: G11C11/34

CPC classification number: G11C16/3427 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454

Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

Abstract translation: 本公开涉及内存扭结检查。 一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。 至少部分地由于施加到第一数据线的电压和至少第一数据线和第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到 第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。 响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。

公开(公告)号：US20140189465A1

公开(公告)日：2014-07-03

申请号：US14109375

申请日：2013-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mark A. Helm ,  Uday Chandrasekhar

IPC: G11C16/28 ,  G06F11/10 ,  H03M13/05

CPC classification number: G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Abstract translation: 本公开包括用于数据感测的方法和装置。 一种这样的方法包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测操作的数量的连续感测操作之间改变状态的数量存储器单元的数量，以及确定 至少部分地基于确定在连续感测操作之间改变状态的存储器单元的数量的确定数量，是否输出对应于多个连续感测操作中的一个的硬数据。

公开(公告)号：US20130294156A1

公开(公告)日：2013-11-07

申请号：US13938078

申请日：2013-07-09

Applicant: Micron Technology, Inc.

Inventor： Uday Chandrasekhar ,  Mark A. Helm

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454

Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

Abstract translation: 本公开涉及内存扭结检查。 一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。 至少部分地由于施加到第一数据线的电压和至少第一数据线和第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到 第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。 响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。