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公开(公告)号：US11599416B1
公开(公告)日：2023-03-07
申请号：US17464290
申请日：2021-09-01
发明人： Jianmin Huang , Xiangang Luo , Kulachet Tanpairoj
摘要： An apparatus includes a media management superblock component. The media management superblock component determines that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component compares the quantity of bad blocks to a bad block criteria. The media management superblock component writes host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.
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公开(公告)号：US20230069159A1
公开(公告)日：2023-03-02
申请号：US17464290
申请日：2021-09-01
发明人： Jianmin Huang , Xiangang Luo , Kulachet Tanpairoj
摘要： An apparatus includes a media management superblock component. The media management superblock component determines that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component compares the quantity of bad blocks to a bad block criteria. The media management superblock component writes host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.
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公开(公告)号：US20230061800A1
公开(公告)日：2023-03-02
申请号：US17464316
申请日：2021-09-01
IPC分类号： G06F3/06
摘要： A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.
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公开(公告)号：US20220413699A1
公开(公告)日：2022-12-29
申请号：US17362542
申请日：2021-06-29
发明人： Xiangang Luo , Ashutosh Malshe , Huachen Li , Giuseppe D'eliseo , Jianmin Huang
IPC分类号： G06F3/06
摘要： An apparatus can include a partial superblock memory management component. The partial superblock memory management component can identify bad blocks in respective planes of a block of non-volatile memory cells. The partial superblock memory management component can determine that a plane of the respective planes includes at least good block in at least one different block of non-volatile memory cells. The partial superblock memory management component can perform an operation to reallocate the at least one good block in the plane to the at least one bad block in the plane to form blocks of non-volatile memory cells having a quantity of bad blocks that satisfies a bad block threshold.
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公开(公告)号：US11520491B2
公开(公告)日：2022-12-06
申请号：US17228086
申请日：2021-04-12
发明人： Xiangang Luo , Zhengang Chen
IPC分类号： G06F3/06
摘要： A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.
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公开(公告)号：US11475974B2
公开(公告)日：2022-10-18
申请号：US17393886
申请日：2021-08-04
摘要： Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
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公开(公告)号：US20220269559A1
公开(公告)日：2022-08-25
申请号：US17741940
申请日：2022-05-11
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US11409446B2
公开(公告)日：2022-08-09
申请号：US17095386
申请日：2020-11-11
发明人： Tao Liu , Xiangang Luo
IPC分类号： G06F3/06
摘要： A method includes detecting a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of memory cells associated therewith, responsive to detecting the power-up event and prior to receipt of signaling indicative of a host initiation sequence, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells, determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value, and selectively performing a media management operation of a respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block exhibits greater than the threshold health characteristic value.
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公开(公告)号：US11321173B2
公开(公告)日：2022-05-03
申请号：US16854429
申请日：2020-04-21
摘要： Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.
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公开(公告)号：US20220083243A1
公开(公告)日：2022-03-17
申请号：US16948305
申请日：2020-09-11
发明人： Kishore Kumar Muchherla , Karl D. Schuh , Jiangang Wu , Mustafa N. Kaynak , Devin M. Batutis , Xiangang Luo
IPC分类号： G06F3/06
摘要： A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.
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