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    VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE
    1.
    发明申请
    VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE 有权

    公开(公告)号：US20220300186A1

    公开(公告)日：2022-09-22

    申请号：US17203474

    申请日：2021-03-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kishore Kumar Muchherla ,  Devin M. Batutis ,  Xiangang Luo ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Shane Nowell

    IPC: G06F3/06

    Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

    Multi-tier threshold voltage offset bin calibration
    2.
    发明授权
    Multi-tier threshold voltage offset bin calibration 有权

    公开(公告)号：US11450391B2

    公开(公告)日：2022-09-20

    申请号：US16948359

    申请日：2020-09-15

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

    IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/04

    Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

    SELECTIVE PARTITIONING OF SETS OF PAGES PROGRAMMED TO MEMORY DEVICE
    6.
    发明申请
    SELECTIVE PARTITIONING OF SETS OF PAGES PROGRAMMED TO MEMORY DEVICE 有权

    公开(公告)号：US20220083243A1

    公开(公告)日：2022-03-17

    申请号：US16948305

    申请日：2020-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

    IPC: G06F3/06

    Abstract: A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.

    SELECT GATE MAINTENANCE IN A MEMORY SUB-SYSTEM
    7.
    发明申请
    SELECT GATE MAINTENANCE IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210233594A1

    公开(公告)日：2021-07-29

    申请号：US17301743

    申请日：2021-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Devin M. Batutis ,  Avinash Rajagiri ,  Sheng-Huang Lee ,  Chun Sum Yeung ,  Harish R. Singidi

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

    Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

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