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    ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM
    13.
    发明公开
    ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20230386583A1

    公开(公告)日：2023-11-30

    申请号：US17752590

    申请日：2022-05-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/32 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/32 ,  G11C16/10 ,  G11C16/349 ,  G11C16/0483

    Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.

    MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM
    14.
    发明申请
    MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM 有权

    公开(公告)号：US20250166696A1

    公开(公告)日：2025-05-22

    申请号：US19030522

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

    Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

    CONCURRENT READ ERROR HANDLING OPERATIONS
    15.
    发明申请
    CONCURRENT READ ERROR HANDLING OPERATIONS 有权

    公开(公告)号：US20250110827A1

    公开(公告)日：2025-04-03

    申请号：US18782536

    申请日：2024-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Methods, systems, and devices for concurrent read error handling operations are described. A system may perform a read error handling procedure in which operations may be performed concurrently or in succession. For example, a second read operation may be initiated while error control is being performed for a first read operation, or while data from the first read operation is being transferred to a controller. Further, the second read operation may be terminated based on identifying one or more errors in the data from the first read operation, such that the read error handling procedure may be terminated without finishing active processes of the read error handling procedure. Additionally, the system may be configured to perform the read error handling procedure such that a channel activation operation and a channel deactivation operation may be performed at the beginning and end of the read error handling procedure, respectively.

    Memory device with fast write mode to mitigate power loss
    17.
    发明授权
    Memory device with fast write mode to mitigate power loss 有权

    公开(公告)号：US12254926B2

    公开(公告)日：2025-03-18

    申请号：US17817288

    申请日：2022-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Juane Li ,  Sead Zildzic, Jr. ,  Zhenming Zhou

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

    Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

    ENHANCING READ WINDOW BUDGET USING READ VERIFY
    18.
    发明申请
    ENHANCING READ WINDOW BUDGET USING READ VERIFY 有权

    公开(公告)号：US20250069675A1

    公开(公告)日：2025-02-27

    申请号：US18774642

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Zhang ,  Yu-Chung Lien ,  Peng Zhang ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32

    Abstract: The disclosure configures a memory sub-system controller to use prior read verify operations to selectively apply enhancements to read window budgets (RWB). The controller receives a request to perform a memory operation on data stored in an individual memory component of a set of memory components. The controller accesses RWB tracking information associated with the individual memory component and determines that the tracking information associated with the individual memory component indicates a need for enhancing a RWB associated with the memory operation. The controller applies one or more enhancement processes to the individual memory component in response to determining that the tracking information associated with the individual memory component indicates the need for enhancing the RWB associated with the memory operation.

    MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM
    20.
    发明申请
    MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20240411449A1

    公开(公告)日：2024-12-12

    申请号：US18646266

    申请日：2024-04-25

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Tomer Tzvi Eliash ,  Zhenming Zhou

    IPC: G06F3/06

    Abstract: A processing device, operatively coupled with a memory device, performs a first sequence of programming operations on a first set of cells addressable by a first wordline of the memory device. The processing device identifies a second wordline of the memory device, wherein a second physical location of the second wordline is in a predefined relationship with a first physical location of the first wordline. The processing device performs a second sequence of programming operations on a second set of cells addressable by the second wordline of the first die, wherein a first order of the first sequence of programming operations is different from a second order of the second sequence of programming operations.

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