公开(公告)号：US11720489B2

公开(公告)日：2023-08-08

申请号：US17902384

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

IPC: G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20220188018A1

公开(公告)日：2022-06-16

申请号：US17688304

申请日：2022-03-07

Applicant: Micron Technology, Inc.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US20210383872A1

公开(公告)日：2021-12-09

申请号：US17409413

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Luigi Esposito ,  Massimo Iaculo ,  Eric Kwok Fung Yuen ,  Gerard J. Perdaems

IPC: G11C16/10 ,  G06F3/06 ,  G06F11/07

Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit, The memory controller may also store an indication that the first storage sub-unit is invalid.

公开(公告)号：US20210141557A1

公开(公告)日：2021-05-13

申请号：US16075464

申请日：2017-12-21

Applicant: MICRON TECHNOLOGY INC.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US20200371719A1

公开(公告)日：2020-11-26

申请号：US16990864

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Angelo Della Monica ,  Eric Kwok Fung Yuen ,  Pasquale Cimmino ,  Massimo Iaculo ,  Francesco Falanga

IPC: G06F3/06

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10725904B2

公开(公告)日：2020-07-28

申请号：US16075543

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F12/02 ,  G06F12/0873

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

公开(公告)号：US11620216B2

公开(公告)日：2023-04-04

申请号：US17750933

申请日：2022-05-23

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Guanzhong Wang ,  Xu Zhang ,  Eric Kwok Fung Yuen

IPC: G11C16/26 ,  G06F12/06 ,  G06F12/0893 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

公开(公告)号：US20220283939A1

公开(公告)日：2022-09-08

申请号：US17750933

申请日：2022-05-23

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Guan Zhong Wang ,  Xu Zhang ,  Eric Kwok Fung Yuen

IPC: G06F12/06 ,  G06F12/0893 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

公开(公告)号：US11341048B2

公开(公告)日：2022-05-24

申请号：US16488718

申请日：2018-10-29

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Guanzhong Wang ,  Xu Zhang ,  Eric Kwok Fung Yuen

IPC: G11C11/56 ,  G06F12/06 ,  G06F12/0893 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

公开(公告)号：US20220011936A1

公开(公告)日：2022-01-13

申请号：US17486420

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guanzhong Wang ,  Xinghui Duan ,  Hua Chen Li

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entityp, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.