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165 条记录 (耗时 0.03 秒)

    Semiconductor device and method for manufacturing the same
    11.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08134209B2

    公开(公告)日：2012-03-13

    申请号：US12640658

    申请日：2009-12-17

    申请人： Atsushi Yagishita ,  Makoto Fujiwara ,  Hirohisa Kawasaki ,  Mariko Takayanagi

    发明人： Atsushi Yagishita ,  Makoto Fujiwara ,  Hirohisa Kawasaki ,  Mariko Takayanagi

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

    摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

    摘要翻译： 提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。 多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。 浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。 多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

    CARD HOST LSI AND SET DEVICE INCLUDING THE SAME
    13.
    发明申请
    CARD HOST LSI AND SET DEVICE INCLUDING THE SAME 有权
    卡主机LSI和集成设备，包括它们

    公开(公告)号：US20100318690A1

    公开(公告)日：2010-12-16

    申请号：US12861569

    申请日：2010-08-23

    申请人： Takehisa Hirano ,  Makoto Fujiwara ,  Koichiro Fue ,  Rie Itou ,  Kentaro Shiomi

    发明人： Takehisa Hirano ,  Makoto Fujiwara ,  Koichiro Fue ,  Rie Itou ,  Kentaro Shiomi

    IPC分类号： G06F3/00 ,  G06F13/00

    CPC分类号： G06F13/385

    摘要： In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.

    摘要翻译： 在具有卡主机LSI的集合装置中，实现了到可移除卡等的高速数据传输，而不会妨碍尺寸和重量的减小。 卡主机LSI和可拆卸卡连接到符合预定卡总线规格的卡总线。 微型计算机模块和卡主机LSI也通过符合预定卡总线规格的卡总线连接。

    LSI design method and verification method
    18.
    发明授权
    LSI design method and verification method 有权
    LSI设计方法和验证方法

    公开(公告)号：US07281136B2

    公开(公告)日：2007-10-09

    申请号：US09779440

    申请日：2001-02-09

    申请人： Kentaro Shiomi ,  Akira Motohara ,  Makoto Fujiwara ,  Toshiyuki Yokoyama ,  Katsuya Fujimura

    发明人： Kentaro Shiomi ,  Akira Motohara ,  Makoto Fujiwara ,  Toshiyuki Yokoyama ,  Katsuya Fujimura

    IPC分类号： G06F12/14 ,  G06F17/50

    CPC分类号： G06F21/75 ,  G06F17/5022 ,  G06F21/6209

    摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

    摘要翻译： 在LSI设计中采用加密处理，以便改进电路设计数据对传统示例的保密性。 在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。 将加密的设计数据提供给进行设计/验证处理的用户。 钥匙也按要求提供。 在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。 在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。

    Encryption circuit
    19.
    发明申请
    Encryption circuit 审中-公开
    加密电路

    公开(公告)号：US20050271201A1

    公开(公告)日：2005-12-08

    申请号：US11133289

    申请日：2005-05-20

    申请人： Kazuya Shimizu ,  Tomoya Sato ,  Kentaro Shiomi ,  Yusuke Nemoto ,  Yuishi Torisaki ,  Makoto Fujiwara

    发明人： Kazuya Shimizu ,  Tomoya Sato ,  Kentaro Shiomi ,  Yusuke Nemoto ,  Yuishi Torisaki ,  Makoto Fujiwara

    IPC分类号： H04L9/10 ,  G06K19/073 ,  H04K1/00 ,  H04L9/06

    CPC分类号： H04L9/0625 ,  H04L9/004 ,  H04L2209/12

    摘要： An encryption circuit of a secret key cryptosystem which inputs a plain text and a secret key 4A, inputs R partial keys Kn obtained from the secret key 4A and applies repeatedly R times of round operations to the plain text so that the plain text is encrypted including: registers 4G and 4H which store the values after the round operations of the plain text; a fault detection circuit 1A which decides whether a degenerate fault exists or not by the values of the registers 4G and 4H; and a circuit 1B which invalidates the secret key 4A when the degenerate fault exists in the detection result. The invention provides an encryption circuit which can appropriately respond to a new element of causing occurrence of the degenerate fault, suppress the cost of the hardware, and has a measure against the fault analysis while suppressing an increase in an encryption processing time.

    摘要翻译： 输入明文和秘密密钥4A的秘密密钥密码系统的加密电路输入从秘密密钥4A获得的R个部分密钥Kn，并且对明文重复地应用R次循环操作，使得明文是 加密包括：寄存器4G和4H，其在明文的循环操作之后存储值; 故障检测电路1A，其通过寄存器4G和4H的值判定退化故障是否存在; 以及当检测结果中存在退化故障时使秘密密钥4A无效的电路1B。 本发明提供了一种加密电路，其可以适当地响应引起退化故障的发生的新元件，抑制硬件的成本，并且在抑制加密处理时间的增加的同时具有针对故障分析的措施。

    Bus structure, database and method of designing interface
    20.
    发明申请
    Bus structure, database and method of designing interface 审中-公开

    公开(公告)号：US20050246667A1

    公开(公告)日：2005-11-03

    申请号：US11172905

    申请日：2005-07-05

    申请人： Makoto Fujiwara

    发明人： Makoto Fujiwara

    IPC分类号： G06F3/00 ,  G06F9/45 ,  G06F13/10 ,  G06F13/14 ,  G06F13/36 ,  G06F13/38 ,  G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G06F17/5045

    摘要： With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered. In a performance table of each library, the performance index of the library is expressed as a function of parameters of throughput, a bus width, instruction quantity and memory size. Also, a portion of the operation realized by using software and a portion realized by using hardware are registered. Through operation simulation conducted with each application successively replaced with each of the libraries, the performance of a semiconductor integrated circuit can be evaluated, so as to synthesize an optimal interface.