公开(公告)号：US06941440B2

公开(公告)日：2005-09-06

申请号：US10439297

申请日：2003-05-15

申请人： Laurent R. Moll ,  James D. Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph B. Rowlands

发明人： Laurent R. Moll ,  James D. Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph B. Rowlands

IPC分类号： G06F3/00 ,  G06F9/42 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1684

摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

公开(公告)号：US07490187B2

公开(公告)日：2009-02-10

申请号：US10742060

申请日：2003-12-20

申请人： Laurent R. Moll ,  Manu Gulati

发明人： Laurent R. Moll ,  Manu Gulati

IPC分类号： G06F13/20

CPC分类号： G06F13/423

摘要： A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. The training sequence may received during startup or reset, immediately after startup or reset completes, or may be received periodically during training intervals.

摘要翻译： 双模式数字接口支持超传输标准和至少一种其他接口标准。 双模数字接口包括物理接口，多个数据线放大器，时钟线放大器，多个数据线去歪斜/采样块，数据组歪斜模块和启用控制模块。 多个数据线去歪斜/采样块基于时钟信号在相应数据线上进行去歪斜和采样输入数据以产生偏斜数据。 数据组去偏移模块从多个数据线去歪斜/采样块中的每一个接收偏斜数据，并从数据交换数据中移出数据线偏移以产生接收到的数据。 可以基于从链路伙伴接收的训练序列来设置多个数据线去歪斜/采样块和数据组歪斜模块。 训练序列可以在启动或复位期间立即在启动或复位完成之后接收，或者可以在训练间隔期间周期性接收。

公开(公告)号：US07319702B2

公开(公告)日：2008-01-15

申请号：US10684998

申请日：2003-10-14

申请人： Laurent R. Moll ,  Manu Gulati

发明人： Laurent R. Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： G06F13/4018

摘要： A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the fragment to combine with a next segment for alignment of data. A buffer receives the aligned data from the data aligner for interim storage and subsequent output onto an internal data path.

摘要翻译： 数据对齐器对齐具有小于内部数据路径的宽度的粒度的数据段。 数据对齐器对齐数据片段以与当前片段对齐，或将片段延迟与下一片段组合，以便对齐数据。 缓冲器从数据对准器接收对准的数据，用于临时存储和后续输出到内部数据路径。

公开(公告)号：US07596148B2

公开(公告)日：2009-09-29

申请号：US11786275

申请日：2007-04-11

申请人： Manu Gulati ,  Laurent R. Moll ,  James B. Keller

发明人： Manu Gulati ,  Laurent R. Moll ,  James B. Keller

IPC分类号： H04L12/28

CPC分类号： G06F13/4247

摘要： A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

摘要翻译： 用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段，其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段，并且其中数据段 所述多个数据段对应于所述多路复用数据片段中的一个。 该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。 该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。 该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

公开(公告)号：US06748479B2

公开(公告)日：2004-06-08

申请号：US10270029

申请日：2002-10-11

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F1300

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US09378150B2

公开(公告)日：2016-06-28

申请号：US13406905

申请日：2012-02-28

申请人： Rohit K. Gupta ,  Manu Gulati

发明人： Rohit K. Gupta ,  Manu Gulati

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/6028 ,  G06F2212/654

摘要： Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.

摘要翻译： 公开了涉及实现虚拟存储器的集成电路的技术。 在一个实施例中，公开了一种集成电路，其包括被配置为存储非预取的翻译的翻译后备缓冲器和被配置为存储预取的翻译的翻译表。 在这样的实施例中，翻译后备缓冲器和翻译表共享表行走电路。 在一些实施例中，表走路电路被配置为响应于预取请求而在转换表中存储转换，并且不更新转换后备缓冲器。 在一些实施例中，翻译后备缓冲器，转换表和行走电路被包括在存储器管理单元内，该存储器管理单元经配置以经由多个直接存储器访问（DMA）通道来服务从多个客户端电路接收的存储器请求。

公开(公告)号：US20140052929A1

公开(公告)日：2014-02-20

申请号：US13590150

申请日：2012-08-20

申请人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

发明人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  Y02D10/13

摘要： A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

摘要翻译： 一种用于高效监控嵌入式系统中多个组件的跟踪的系统和方法。 系统级芯片（SOC）包括用于收集和存储跟踪历史，总线事件统计信息或两者的跟踪单元。 SOC可以在共享存储器和高速缓存一致控制器之间的多个总线上传送高速缓存相干消息。 跟踪单元包括多个总线事件过滤器。 可编程配置寄存器用于将总线事件滤波器分配给选定的总线，用于监视相关的总线流量并确定是否发生合格的总线事件。 如果是这样，总线事件过滤器会为每个合格的总线事件增加相关的计数。 用于确定合格总线事件的值可以由可编程配置寄存器设置。

公开(公告)号：US20130346800A1

公开(公告)日：2013-12-26

申请号：US13533295

申请日：2012-06-26

申请人： Manu Gulati ,  James D. Ramsay ,  Erik P. Machnicki ,  Jianlin Yu

发明人： Manu Gulati ,  James D. Ramsay ,  Erik P. Machnicki ,  Jianlin Yu

IPC分类号： G06F11/273

CPC分类号： G06F11/27

摘要： In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.

摘要翻译： 在一个实施例中，SOC包括多个组件，包括CPU复合体和一个或多个非CPU组件，例如外围接口控制器，存储器控制器，媒体组件等.SAC还包括SOC调试控制单元，其被耦合以接收 从组件检测到调试事件。 每个组件可以包括本地调试控制单元，其被配置为监视该组件内的各种调试事件。 调试事件可能是组件特有的。 本地调试控制单元可以将检测到的事件发送到SOC调试控制单元。 SOC调试控制单元可以从一个或多个组件检测一个或多个事件，并且可以响应于检测所选择的事件而停止SOC的组件。

公开(公告)号：US20070189299A1

公开(公告)日：2007-08-16

申请号：US11786275

申请日：2007-04-11

申请人： Manu Gulati ,  Laurent Moll ,  James Keller

发明人： Manu Gulati ,  Laurent Moll ,  James Keller

IPC分类号： H04L12/56 ,  H04L12/54

CPC分类号： G06F13/4247

摘要： A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

摘要翻译： 用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段，其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段，并且其中数据段 所述多个数据段对应于所述多路复用数据片段中的一个。 该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。 该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。 该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

公开(公告)号：US07171521B2

公开(公告)日：2007-01-30

申请号：US11182123

申请日：2005-07-15

申请人： Joseph B. Rowlands ,  Manu Gulati

发明人： Joseph B. Rowlands ,  Manu Gulati

IPC分类号： G06F13/00

CPC分类号： G06F12/084 ,  G06F12/0824

摘要： A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; and facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link.

摘要翻译： 共享存储器系统包括多个处理节点和分组化的输入/输出链路。 多个处理节点中的每一个包括处理资源和存储器。 打包的I / O链路将多个处理节点可操作地耦合在一起。 多个处理节点中的一个可操作地耦合到：发起相干存储器事务，使得多个处理节点中的另一个处理节点可以访问多个处理节点之一的存储器的归属存储器部分; 并且便于通过分组化的I / O链路在多个处理节点之一的存储器与多个处理节点中的另一个处理节点之间传输一致性事务分组。