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    Domino circuits with high performance and high noise immunity
    11.
    发明授权
    Domino circuits with high performance and high noise immunity 有权
    具有高性能和高抗噪声能力的多米诺电路

    公开(公告)号：US06204696B1

    公开(公告)日：2001-03-20

    申请号：US09158410

    申请日：1998-09-22

    申请人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    发明人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.

    摘要翻译： 在一些实施例中，本发明包括具有预充电电路的多米诺骨牌电路，该预充电电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 评估路径电路也耦合到多米诺骨牌导体。 迟滞输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有耦合到多米诺骨牌导体的预放电电路的多米诺骨牌电路。 评估路径电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 滞后输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有预充电电路的多米诺骨牌电路，其包括耦合到多米诺骨牌导体。 评估路径电路耦合到多米诺骨牌导体。 输出级包括反相器，用于从多米诺骨架导体接收信号并在输出导体上提供评估输出信号，输出级包括耦合到输出导体的重复评估路径电路。

    Adaptively extending tunable range of frequency in a closed loop
    12.
    发明授权
    Adaptively extending tunable range of frequency in a closed loop 有权
    在闭环中自适应地扩展频率的可调范围

    公开(公告)号：US07119628B2

    公开(公告)日：2006-10-10

    申请号：US10985511

    申请日：2004-11-10

    申请人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03L7/08

    CPC分类号： H03L7/18 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107

    摘要： A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.

    摘要翻译： 半导体器件或电路包括可控振荡器和电路，其感测可控制可控振荡器并且数字控制增益补偿的电压，自适应地补偿增益中的下降与闭环内的整体环路增益。 在一个实施例中，可以使用单个供电源为闭环供电，而可数字控制的可变增益级可以基于该下降以前馈方式调节增益。

    Single ended interconnect systems
    16.
    发明授权
    Single ended interconnect systems 失效
    单端互连系统

    公开(公告)号：US06617892B2

    公开(公告)日：2003-09-09

    申请号：US09157089

    申请日：1998-09-18

    申请人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    发明人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath

    IPC分类号： H03B100

    CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

    摘要： In some embodiments, the invention includes an interconnect system having a single ended driver and a single ended hysteretic receiver. A single ended interconnect is coupled between the single ended driver and single ended receiver. In other embodiments, the invention involves an interconnect system including interconnects, single ended drivers, and single ended hysteretic receivers connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals and an enable signal and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted. In yet other embodiments, the invention includes an interconnect system having interconnects, quasi-static drivers and receivers connected to respective ones of the interconnects. The quasi-static drivers to transmit interconnect signals on the interconnects, the quasi-static drivers receive a clock signal and respective data-in signals, and wherein the interconnect signals are pre-discharge when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals. In still other embodiments, the invention includes a pseudo differential interconnect system and an interconnect system with a dual rail driver.

    摘要翻译： 在一些实施例中，本发明包括具有单端驱动器和单端滞后接收器的互连系统。 单端互连连接在单端驱动器和单端接收器之间。 在其他实施例中，本发明涉及一种互连系统，包括互连，单端驱动器和连接到相应的互连的单端滞后接收器。 单端驱动器接收相应的数据输入信号和使能信号，并且其中当使能信号被断言时，驱动器在互连上发送互连信号。 在其他实施例中，本发明包括具有互连的互连系统，准静态驱动器和连接到相应的互连的接收器。 用于在互连上传输互连信号的准静态驱动器，准静态驱动器接收时钟信号和相应的数据输入信号，并且其中当时钟信号从第一状态变为第二状态时，互连信号是预放电的 ，并且其中当所述时钟信号处于所述第一状态时，所述互连信号与所述数据输入信号相关。 在其他实施例中，本发明包括伪差分互连系统和具有双轨驱动器的互连系统。

    Method and apparatus for obtaining linear code-delay response from area-efficient delay cells
    17.
    发明授权
    Method and apparatus for obtaining linear code-delay response from area-efficient delay cells 有权
    用于从区域有效的延迟单元获得线性码延迟响应的方法和装置

    公开(公告)号：US06417714B1

    公开(公告)日：2002-07-09

    申请号：US09539732

    申请日：2000-03-30

    申请人： Ahmed Biyabani ,  Krishnamurthy Soumyanath

    发明人： Ahmed Biyabani ,  Krishnamurthy Soumyanath

    IPC分类号： H03H1126

    CPC分类号： H03K5/086 ,  H03K3/3565 ,  H03K5/131 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00234 ,  H03L7/0814

    摘要： An area-efficient delay cell utilizes transistor stacks to control positive feedback responsive to a counter code, thereby controlling the hysteresis and overall signal delay of the cell. The code-delay response of the cell can be modified by freezing the counter code at a convenient value. Linear superposition of the responses of one modified cell connected in series with one unmodified cell provides a more linear overall response and reduces jitter when used in a delay locked loop.

    摘要翻译： 区域有效的延迟单元利用晶体管堆栈来响应于计数器代码来控制正反馈，从而控制单元的滞后和整体信号延迟。 可以通过以适当的值冻结计数器代码来修改单元的代码延迟响应。 与一个未修改的单元串联连接的一个修改单元的响应的线性叠加提供更线性的总体响应，并且当在延迟锁定环路中使用时减少抖动。

    Boosted multiplexer transmission gate
    18.
    发明授权
    Boosted multiplexer transmission gate 有权
    升压复用器传输门

    公开(公告)号：US06404237B1

    公开(公告)日：2002-06-11

    申请号：US09752063

    申请日：2000-12-29

    申请人： Sanu Mathew ,  Ram Krishnamurthy ,  Krishnamurthy Soumyanath

    发明人： Sanu Mathew ,  Ram Krishnamurthy ,  Krishnamurthy Soumyanath

    IPC分类号： H03K19094

    CPC分类号： H03K17/6872 ,  H03K17/063 ,  H03K17/693

    摘要： An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS transistors of a transmission gate to turn on the transistors more strongly and speed the passage of data signals.

    摘要翻译： 一种用于通过对一对电容器充电并且使用该对电容器的耦合效应来过载驱动传输门极的NMOS和PMOS晶体管的栅极输入以更强烈地导通晶体管并加速通路的装置和方法 的数据信号。

    Single ended domino compatible dual function generator circuits
    19.
    发明授权
    Single ended domino compatible dual function generator circuits 失效
    单端多米诺骨牌兼容双功能发生器电路

    公开(公告)号：US06225826B1

    公开(公告)日：2001-05-01

    申请号：US09220816

    申请日：1998-12-23

    申请人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath ,  Mark A. Anders

    发明人： Ram K. Krishnamurthy ,  Krishnamurthy Soumyanath ,  Mark A. Anders

    IPC分类号： H03K19096

    CPC分类号： H03K19/096 ,  H03K19/0963

    摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.

    摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。