-
11.发明授权公开(公告)号：US07105903B2
公开(公告)日：2006-09-12
申请号：US10993196
申请日：2004-11-18
申请人： Brian R. Butcher , Gregory W. Grynkewich , Kelly W. Kyler , Kenneth H. Smith , Richard G. Williams
发明人： Brian R. Butcher , Gregory W. Grynkewich , Kelly W. Kyler , Kenneth H. Smith , Richard G. Williams
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L29/82 , H01L43/00
CPC分类号： H01L43/12 , H01L27/226
摘要： Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.
摘要翻译： 提供了用于与半导体元件的上覆电极的电连通的结构以及用于制造这种结构的方法。 与上覆电极电连通的结构包括具有横向尺寸的第一电极，覆盖第一电极的半导体元件和覆盖半导体元件的第二电极。 第二电极具有小于第一电极的横向尺寸的横向尺寸。 导电硬掩模覆盖在第二电极上并且与第二电极电连通。 导电硬掩模具有基本上等于第一电极的横向尺寸的横向尺寸。 导电接触元件与导电硬掩模电连通。
-
公开(公告)号：US06334929B1
公开(公告)日：2002-01-01
申请号：US08282295
申请日：1994-07-29
IPC分类号： B44C122
CPC分类号： H01L21/31116
摘要： A process for improving uniformity across the surface of a substrate during a plasma process such as plasma etching. A conductive plane is formed at the back surface of the substrate. A plasma process is then performed to the front surface of the substrate. The conductive plane may then be removed upon completion of the plasma process and before final processing steps.
摘要翻译： 一种在诸如等离子体蚀刻的等离子体工艺期间改善衬底表面的均匀性的方法。 在基板的背面形成导电平面。 然后对基板的前表面进行等离子体处理。 然后可以在完成等离子体处理之后和在最终处理步骤之前去除导电平面。
-
搜索结果
12 条记录 (耗时 0.027 秒)
