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11.发明授权Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies 有权具有混合和超低电压电源的高速技术的静电放电保护结构公开(公告)号：US06768616B2
公开(公告)日：2004-07-27
申请号：US10099600
申请日：2002-03-15
IPC分类号： H02H322
CPC分类号： H01L27/0262 , H01L27/0251 , H01L29/866 , H03K17/0812 , H03K17/0814 , H03K17/305
摘要： An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad, adapted for connection to a protected circuit node of the IC, and an ESD protection device, which is coupled between the pad and ground. A diode turn-on device is coupled in a forward conduction direction from the pad to a first gate of the ESD protection device. In a second embodiment, the ESD protection circuit is an SCR having an anode coupled to a first voltage supply line, and a cathode coupled to ground. A parasitic capacitance is coupled between each the voltage supply line and the grounded cathode.
摘要翻译： 具有保护电路的半导体集成电路（IC）中的静电放电（ESD）保护电路。 在一个实施例中，ESD保护电路包括适于连接到IC的受保护电路节点的焊盘和耦合在焊盘和接地之间的ESD保护装置。 二极管导通装置从正面传导方向耦合到ESD保护装置的第一栅极。 在第二实施例中，ESD保护电路是具有耦合到第一电压供应线的阳极和耦合到地的阴极的SCR。 寄生电容耦合在每个电源线和接地阴极之间。
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12.发明授权Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies 有权用于硅锗技术的静电放电保护硅控整流器（ESD-SCR）公开(公告)号：US06770918B2
公开(公告)日：2004-08-03
申请号：US10238699
申请日：2002-09-10
IPC分类号： H01L2972
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/165 , H01L29/7378 , H01L29/861
摘要： An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N+ doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.
摘要翻译： 一种具有用于保护集成电路（IC）的电路的可控硅整流器（SCR）的静电放电（ESD）保护装置。 SCR包括设置在衬底上的N掺杂层和设置在N掺杂层上的第一P掺杂区。 形成阴极的至少一个第一N +掺杂区域设置在P掺杂区域上并耦合到地。 至少一个第一N +掺杂区，第一P掺杂区和N掺杂层形成SCR的垂直NPN晶体管。 形成阳极的第二P掺杂区域被耦合到受保护的焊盘。 第二P掺杂区域设置在N掺杂层上方，并相对于第一P掺杂区域横向定位并电隔离。 第二P掺杂区，N掺杂层和第一P掺杂区形成SCR的横向PNP晶体管。
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13.发明授权Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on 有权静电放电（ESD）保护装置，具有同时分布的自适应多指开启公开(公告)号：US07372681B2
公开(公告)日：2008-05-13
申请号：US11105103
申请日：2005-04-13
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/0653 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fingered MOS transistor, each finger respectively adapted for coupling between an I/O pad and a first supply line of the IC. An ESD detector is coupled to the I/O pad via a first terminal, and a second terminal is adapted for coupling to a second supply line potential of the IC. A parasitic capacitance is formed between the second supply line potential of the IC and the first supply line potential. A transfer circuit is coupled to a third terminal of the ESD detector and is adapted for biasing at least one gate respectively associated with at least one finger of the multi-fingered MOS transistor.
摘要翻译： 用于在正常操作期间保护IC的核心电路的半导体集成电路（IC）的静电放电（ESD）保护电路，并且在IC的非供电模式期间分流ESD事件。 ESD保护电路包括多指MOS晶体管，每个手指分别适于在IC的I / O焊盘和第一电源线之间耦合。 ESD检测器经由第一端子耦合到I / O焊盘，并且第二端子适于耦合到IC的第二电源线电位。 在IC的第二供电线电位和第一供电线电位之间形成寄生电容。 传输电路耦合到ESD检测器的第三端子，并且适于偏置分别与多指MOS晶体管的至少一个手指相关联的至少一个栅极。
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公开(公告)号：US07414273B2
公开(公告)日：2008-08-19
申请号：US11176975
申请日：2005-07-07
申请人： Russell Mohn , Cong-Son Trinh , Phillip Czeslaw Jozwiak , John Armer , Markus Paul Josef Mergens
发明人： Russell Mohn , Cong-Son Trinh , Phillip Czeslaw Jozwiak , John Armer , Markus Paul Josef Mergens
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/7436 , H01L27/0259 , H01L27/0262 , H01L29/0692 , H01L29/74 , H01L29/87
摘要： A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.
摘要翻译： 具有形成棋盘图案的阳极和阴极的二维可控硅整流器（2DSCR）。 这种图案使给定SCR区域内的阳极与阴极接触长度（有效面积）最大化，即有效地增加SCR宽度。 增加物理SCR区域，增加SCR的当前处理能力。
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15.发明授权Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on 有权静电放电（ESD）保护装置，具有同时分布的自适应多指开启公开(公告)号：US06898062B2
公开(公告)日：2005-05-24
申请号：US10822912
申请日：2004-04-12
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H02H9/00
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/0653 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.
摘要翻译： 具有受保护电路的半导体集成电路（IC）的ESD保护电路包括具有至少一个手指的SCR。 每个手指包括PNP晶体管和NPN晶体管，其中PNP和NPN晶体管的发射极分别耦合在IC的I / O焊盘和地之间，PNP晶体管的基极耦合到NPN晶体管的集电极 ，并且NPN晶体管的基极耦合到PNP晶体管的集电极。 每个手指的NPN晶体管还包括用于触发所述手指的第一门。 PMOS晶体管包括分别耦合到IC的I / O焊盘和NPN晶体管的第一栅极的源极和漏极。 此外，PMOS晶体管的栅极耦合到IC的电源电压。
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公开(公告)号：US07763940B2
公开(公告)日：2010-07-27
申请号：US11303054
申请日：2005-12-15
IPC分类号： H01L23/62
CPC分类号： H01L27/027
摘要： An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.
摘要翻译： 具有LV-阱元件触发结构的电子器件，其减少MOS驱动器或ESD保护器件中的有效快速恢复触发电压。 降低的触发电压有助于多手指开启，从而均匀的电流流动和/或有助于避免竞争性触发问题。
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公开(公告)号：US20140167099A1
公开(公告)日：2014-06-19
申请号：US14004182
申请日：2012-03-09
IPC分类号： H01L29/87
CPC分类号： H01L29/87 , H01L27/0262
摘要： An integrated circuit includes a protected circuit. The integrated circuit further includes a silicon controlled rectifier including a sequence of a first p-type region, a second n-type region, a third p-type region and a fourth n-type region. The first n-type region is electrically coupled to the protected circuit. The integrated circuit further includes a first pn junction diode including a first semiconductor zone and one of the group including the second n-type region and the third p-type region as a second semiconductor zone. A conductivity type of the first semiconductor zone is opposite to the conductivity type of the second semiconductor zone. The integrated circuit further includes a first trigger circuit electrically coupled to the first semiconductor zone.
摘要翻译： 集成电路包括受保护的电路。 集成电路还包括可控硅整流器，其包括第一p型区域，第二n型区域，第三p型区域和第四n型区域的序列。 第一n型区域电耦合到受保护的电路。 集成电路还包括第一pn结二极管，其包括第一半导体区和包括第二n型区和第三p型区的组中的一个作为第二半导体区。 第一半导体区的导电类型与第二半导体区的导电类型相反。 集成电路还包括电耦合到第一半导体区的第一触发电路。
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