公开(公告)号：US20060258126A1

公开(公告)日：2006-11-16

申请号：US10544310

申请日：2003-02-06

申请人： Ichiro Shiono ,  Masaharu Ninomiya ,  Hazumu Kougami

发明人： Ichiro Shiono ,  Masaharu Ninomiya ,  Hazumu Kougami

IPC分类号： H01L31/00 ,  H01L21/20

CPC分类号： H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054

摘要： A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed. By this means, the penetrating dislocation density is kept low, surface roughness is low, and worsening of roughness at the surface and at interfaces due to heat treatment in device manufacturing processes or similar is prevented.

摘要翻译： 半导体衬底制造方法具有第一层形成工艺，第二层形成工艺，热处理工艺和抛光工艺; 在第一层形成工艺中，第一SiGe层的厚度被设定为小于临界厚度的两倍，临界厚度是由于增加膜厚而发生位错的膜厚度和晶格弛豫; 在第二层形成工艺中，第二SiGe层的Ge组成比至少在与第一SiGe层或Si层的接触面处设定为低于第一SiGe层中的Ge组成比的最大值 ，并且形成至少部分Ge组成比逐渐朝向表面增加的梯度组成区域。 通过这种方式，穿透位错密度保持较低，表面粗糙度低，并且防止了器件制造过程中类似的热处理在表面和界面处的粗糙度恶化。

公开(公告)号：US20060022200A1

公开(公告)日：2006-02-02

申请号：US10536445

申请日：2002-11-29

申请人： Ichiro Shiono ,  Masaharu Ninomiya ,  Hazumu Kougami

发明人： Ichiro Shiono ,  Masaharu Ninomiya ,  Hazumu Kougami

IPC分类号： H01L29/16 ,  H01L21/20

CPC分类号： H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/155

摘要： In a semiconductor substrate, a field effect transistor, and methods for producing the same, in order to lower threading dislocation density and also to lower surface roughness, a step of repeating, a plurality of times, a process of epitaxially growing a SiGe gradient composition layer of which a Ge composition ratio is gradually increased from a Ge composition ratio of a base material and a process of epitaxially growing a SiGe constant-composition layer on the gradient composition layer at a final Ge composition ratio of the gradient composition layer, thereby depositing a SiGe layer of which a Ge composition ratio changes in a film deposition direction, in a step-like manner with a gradient, a heat treatment step of performing heat treatment at a temperature exceeding a temperature of the epitaxial growth either during or after formation of the SiGe layer, and a polishing step of polishing to remove irregularities on a surface of the SiGe layer which arise in the heat treatment after formation of the SiGe layer are included.

摘要翻译： 为了降低穿透位错密度和降低表面粗糙度，在半导体衬底，场效应晶体管及其制造方法中，重复多次外延生长SiGe梯度组合物的步骤 Ge组成比从基材的Ge组成比逐渐增加的层和在梯度组合物层上以梯度组成层的最终Ge组成比外延生长SiGe恒定组成层的工艺的层，从而沉积 在梯度上以阶梯状的方式，Ge组成比在膜沉积方向上变化的SiGe层，在形成时或之后在超过外延生长温度的温度下进行热处理的热处理步骤 SiGe层，以及抛光步骤，用于去除在热处理后产生的SiGe层的表面上的凹凸 包括SiGe层的形成。

公开(公告)号：US06277193B1

公开(公告)日：2001-08-21

申请号：US09319117

申请日：1999-06-02

申请人： Shinsuke Sadamitsu ,  Tooru Nagashima ,  Yasuo Koike ,  Masaharu Ninomiya ,  Takeshi Kii

发明人： Shinsuke Sadamitsu ,  Tooru Nagashima ,  Yasuo Koike ,  Masaharu Ninomiya ,  Takeshi Kii

IPC分类号： C30B2504

CPC分类号： H01L21/3225 ,  C30B29/06 ,  C30B33/02

摘要： A method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device by which a gettering ability can be given to an epitaxial wafer in which the formation of BMD is not able to be expected in both low- and high-temperature device manufacturing processes, with the manufacturing processes being lower and higher than 1,050° C. in temperature, and has a specific resistance of ≧10 m&OHgr;·cm. When this method is used, such BMD that is sufficient to obtain gettering can be formed in both the low- and high-temperature processes, with the manufacturing processes being lower and higher than 1,050° C. in temperature, even in the epitaxial wafer having a specific resistance of ≧10 m&OHgr;·cm by performing low-temperature heat treatment at 650˜900° C. before starting epitaxial film formation, by selecting the heat-treating time in accordance with the process temperature in the device manufacturing processes and heavy-metal contaminants which are mixed in during the device manufacturing processes can be gettered sufficiently. Therefore, the characteristic deterioration of a device can be prevented and the yield of the device can be improved.

摘要翻译： 一种制造半导体硅外延晶片和半导体器件的方法，通过该方法可以在其中在低温和高温器件制造工艺中不能期望形成BMD的外延晶片获得吸杂能力，其中制造 工艺温度低于1050℃，电阻率> 10mOMEGA.cm。 当使用这种方法时，可以在低温和高温工艺中形成足以获得吸气的这种BMD，其制造工艺在温度下低于1050℃，甚至在具有 通过在开始外延膜形成之前，在650〜900℃进行低温热处理，通过根据器件制造工艺中的工艺温度选择热处理时间和重的电阻值> 10mOMEGA.cm 在器件制造过程中混合的金属污染物可以充分吸收。 因此，可以防止器件的特性劣化，并且可以提高器件的产量。