公开(公告)号：US07682858B2

公开(公告)日：2010-03-23

申请号：US11151526

申请日：2005-06-14

申请人： Yusuke Nagai ,  Satoshi Kobayashi ,  Masaru Nakamura

发明人： Yusuke Nagai ,  Satoshi Kobayashi ,  Masaru Nakamura

IPC分类号： H01L21/00

CPC分类号： H01L21/304 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  H01L21/78 ,  H01L2221/6834

摘要： A wafer processing method for dividing a wafer having function elements in area sectioned by dividing lines formed on the front surface in a lattice pattern into individual chips along the dividing lines, comprising a deteriorated layer forming step for forming a deteriorated layer on the side of the back surface of a position at a distance corresponding to the final thickness of the chip from the front surface of the wafer by applying a laser beam capable of passing through the wafer along the dividing lines from the back surface of the wafer; a dividing step for dividing the wafer into individual chips along the dividing lines by applying external force to the wafer in which the deteriorated layer has been formed along the dividing lines; and a back surface grinding step for grinding the back surface of the wafer divided into individual chips to the final thickness of the chip.

摘要翻译： 一种晶片处理方法，其特征在于，将沿着划分线将在前表面上形成的划分线的划分线的区域的功能元件分割为各个芯片，所述晶片处理方法包括在劣化层形成步骤中形成劣化层 通过施加能够从晶片的背面沿着划分线穿过晶片的激光束，从与晶片的前表面相对应的与芯片的最终厚度相对应的距离的位置的背面; 分割步骤，通过沿着分割线向已经形成有劣化层的晶片施加外力，沿着分割线将晶片分割成单个芯片; 以及后表面研磨步骤，用于将分成单个芯片的晶片的背面研磨至芯片的最终厚度。

公开(公告)号：US20070141811A1

公开(公告)日：2007-06-21

申请号：US11639209

申请日：2006-12-15

申请人： Kazuma Sekiya ,  Masaru Nakamura ,  Satoshi Kobayashi

发明人： Kazuma Sekiya ,  Masaru Nakamura ,  Satoshi Kobayashi

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/00

CPC分类号： H01L21/67092 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  B28D5/0052 ,  B28D5/0094 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

摘要： A method of dividing a wafer having devices which are formed in a plurality of areas sectioned by a plurality of dividing lines formed in a lattice pattern on the front surface, into individual devices along the dividing lines, comprising: a deteriorated layer forming step for forming a deteriorated layer in the inside of the wafer along the dividing lines by applying a laser beam of a wavelength having permeability for the wafer along the dividing lines; a wafer supporting step for putting the rear surface of the wafer on the surface of an adhesive tape which is mounted on an annular frame and whose adhesive strength is reduced by applying ultraviolet radiation thereto; an adhesive strength reducing step for reducing the adhesive strength of the adhesive tape by applying ultraviolet radiation to the adhesive tape to which the wafer has been affixed; and a dividing step for dividing the wafer into individual devices along the dividing lines where the deteriorated layer has been formed by exerting external force to the wafer affixed to the adhesive tape whose adhesive strength has been reduced after the adhesive strength reducing step.

摘要翻译： 一种分割具有形成在由前表面上形成为格子状的多个分割线划分的多个区域中的装置的晶片的分割方法，包括：劣化层形成步骤，用于形成 通过沿分割线施加具有晶片的磁导率的波长的激光束，沿着分割线在晶片内部的劣化层; 晶片支撑步骤，用于将晶片的后表面放置在安装在环形框架上并通过施加紫外线辐射而降低粘合强度的胶带的表面上; 粘合强度降低步骤，通过对已经粘贴所述晶片的粘合带施加紫外线辐射来降低所述粘合带的粘合强度; 以及分割步骤，用于通过对固定到粘合强度已经降低的粘合带上的晶片的外力施加外力，沿着分割线将晶片分割成各个器件。

公开(公告)号：US07449396B2

公开(公告)日：2008-11-11

申请号：US11047585

申请日：2005-02-02

申请人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

发明人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

IPC分类号： H01L21/301

CPC分类号： H01L21/6836 ,  B23K26/40 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  B28D5/0052 ,  H01L21/78 ,  H01L2221/68327

摘要： A method of dividing, along dividing lines, a wafer having function elements formed in areas sectioned by the dividing lines formed in a lattice pattern on the front surface, comprising: a frame holding step for affixing the back surface of the wafer to a dicing tape mounted on an annular frame; a deteriorated layer forming step for forming a deteriorated layer along the dividing lines in the inside of the wafer by applying a pulse laser beam capable of passing through the wafer to the wafer along the dividing lines, from the side of the front surface of the wafer held on the frame; a dividing step for dividing the wafer into individual chips along the dividing lines by exerting external force along the dividing lines where the deteriorated layers have been formed of the wafer held on the frame; an expansion step for enlarging the interval between chips by stretching the dicing tape affixed to the wafer divided into individual chips; and a picking up step for picking up each chip from the expanded dicing tape.

摘要翻译： 沿着分割线划分具有由在前表面上以格子图案形成的分割线划分的区域中形成的功能元件的晶片的方法，包括：框架保持步骤，用于将晶片的背面固定到切割带 安装在环形框架上; 劣化层形成步骤，用于通过从晶片的前表面侧沿分割线施加能够穿过晶片的脉冲激光束沿晶片内部的分割线形成劣化层; 在框架上举行 分割步骤，通过沿着由保持在框架上的晶片形成劣化层的分割线施加外力，沿着分割线将晶片分割成单个芯片; 扩展步骤，用于通过拉伸固定到划分成单个芯片的晶片上的切割带来扩大芯片之间的间隔; 以及用于从扩展的切割胶带拾取每个芯片的拾取步骤。

公开(公告)号：US20050170613A1

公开(公告)日：2005-08-04

申请号：US11047585

申请日：2005-02-02

申请人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

发明人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

IPC分类号： B23K26/00 ,  B23K26/40 ,  B23K101/40 ,  B28D5/00 ,  H01L21/301 ,  H01L21/46 ,  H01L21/68 ,  H01L21/78 ,  H05K3/00

CPC分类号： H01L21/6836 ,  B23K26/40 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  B28D5/0052 ,  H01L21/78 ,  H01L2221/68327

摘要： A method of dividing, along dividing lines, a wafer having function elements formed in areas sectioned by the dividing lines formed in a lattice pattern on the front surface, comprising: a frame holding step for affixing the back surface of the wafer to a dicing tape mounted on an annular frame; a deteriorated layer forming step for forming a deteriorated layer along the dividing lines in the inside of the wafer by applying a pulse laser beam capable of passing through the wafer to the wafer along the dividing lines, from the side of the front surface of the wafer held on the frame; a dividing step for dividing the wafer into individual chips along the dividing lines by exerting external force along the dividing lines where the deteriorated layers have been formed of the wafer held on the frame; an expansion step for enlarging the interval between chips by stretching the dicing tape affixed to the wafer divided into individual chips; and a picking up step for picking up each chip from the expanded dicing tape.

摘要翻译： 沿着分割线划分具有由在前表面上以格子图案形成的分割线划分的区域中形成的功能元件的晶片的方法，包括：框架保持步骤，用于将晶片的背面固定到切割带 安装在环形框架上; 劣化层形成步骤，用于通过从晶片的前表面侧沿分割线施加能够穿过晶片的脉冲激光束沿晶片内部的分割线形成劣化层; 在框架上举行 分割步骤，通过沿着由保持在框架上的晶片形成劣化层的分割线施加外力，沿着分割线将晶片分割成单个芯片; 扩展步骤，用于通过拉伸固定到划分成单个芯片的晶片上的切割带来扩大芯片之间的间隔; 以及用于从扩展的切割胶带拾取每个芯片的拾取步骤。

公开(公告)号：US20050170616A1

公开(公告)日：2005-08-04

申请号：US11047619

申请日：2005-02-02

申请人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

发明人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

IPC分类号： H01L21/304 ,  H01L21/306 ,  H01L21/78 ,  H01L21/301 ,  H01L21/46

CPC分类号： H01L21/3043 ,  H01L21/30625 ,  H01L21/78 ,  H01L2221/68336

摘要： A method of dividing, along dividing lines, a wafer having function elements formed in areas sectioned by the dividing lines formed in a lattice pattern on the front surface, which comprises: a protective member affixing step for affixing a protective member to the front surface of the wafer; a polishing step for polishing the back surface of the wafer having the protective member affixed to the front surface; a deteriorated layer formation step for forming a deteriorated layer along the dividing lines in the inside of the wafer by applying a pulse laser beam capable of passing through the wafer to the wafer along the dividing lines from the polished back surface side of the wafer; a frame holding step for affixing the back surface of the wafer in which the deteriorated layers have been formed along the dividing lines, to a dicing tape mounted on an annular frame; a dividing step for dividing the wafer into individual chips along the dividing lines by exerting external force along the dividing lines where the deteriorated layers have been formed, of the wafer held on the frame; an expansion step for enlarging the interval between chips by stretching the dicing tape affixed to the wafer divided into individual chips; and a pick up step for picking up the chips from the stretched dicing tape.

摘要翻译： 沿着划分线划分具有由在前表面上形成为格子图案的分割线划分的区域中形成的功能元件的晶片的方法，该方法包括：保护构件固定步骤，用于将保护构件固定到 晶圆; 抛光步骤，用于抛光具有固定到前表面的保护构件的晶片的背面; 劣化层形成步骤，通过沿晶片的抛光后表面侧沿分割线施加能够穿过晶片的脉冲激光束，沿着晶片内部的分割线形成劣化层; 用于将已经形成有劣化层的晶片的背面沿分割线固定到安装在环形框架上的切割带的框架保持步骤; 分割步骤，通过沿保持在框架上的晶片沿已经形成有劣化层的划分线施加外力沿分割线将晶片分割成单个芯片; 扩展步骤，用于通过拉伸固定到划分成单个芯片的晶片上的切割带来扩大芯片之间的间隔; 以及从拉伸的切割胶带拾取芯片的拾取步骤。

公开(公告)号：US07179722B2

公开(公告)日：2007-02-20

申请号：US11047619

申请日：2005-02-02

申请人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

发明人： Masahiro Murata ,  Yusuke Nagai ,  Yukio Morishige ,  Satoshi Kobayashi ,  Naoki Ohmiya

IPC分类号： H01L21/301

CPC分类号： H01L21/3043 ,  H01L21/30625 ,  H01L21/78 ,  H01L2221/68336

摘要： A method of dividing, along dividing lines, a wafer having function elements formed in areas sectioned by the dividing lines formed in a lattice pattern on the front surface, which comprises: a protective member affixing step for affixing a protective member to the front surface of the wafer; a polishing step for polishing the back surface of the wafer having the protective member affixed to the front surface; a deteriorated layer formation step for forming a deteriorated layer along the dividing lines in the inside of the wafer by applying a pulse laser beam capable of passing through the wafer to the wafer along the dividing lines from the polished back surface side of the wafer; a frame holding step for affixing the back surface of the wafer in which the deteriorated layers have been formed along the dividing lines, to a dicing tape mounted on an annular frame; a dividing step for dividing the wafer into individual chips along the dividing lines by exerting external force along the dividing lines where the deteriorated layers have been formed, of the wafer held on the frame; an expansion step for enlarging the interval between chips by stretching the dicing tape affixed to the wafer divided into individual chips; and a pick up step for picking up the chips from the stretched dicing tape.

摘要翻译： 沿着划分线划分具有由在前表面上形成为格子图案的分割线划分的区域中形成的功能元件的晶片的方法，该方法包括：保护构件固定步骤，用于将保护构件固定到 晶圆; 抛光步骤，用于抛光具有固定到前表面的保护构件的晶片的背面; 劣化层形成步骤，通过沿晶片的抛光后表面侧沿分割线施加能够穿过晶片的脉冲激光束，沿着晶片内部的分割线形成劣化层; 用于将已经形成有劣化层的晶片的背面沿分割线固定到安装在环形框架上的切割带的框架保持步骤; 分割步骤，通过沿保持在框架上的晶片沿已经形成有劣化层的划分线施加外力沿分割线将晶片分割成单个芯片; 扩展步骤，用于通过拉伸固定到划分成单个芯片的晶片上的切割带来扩大芯片之间的间隔; 以及从拉伸的切割胶带拾取芯片的拾取步骤。

公开(公告)号：US09469001B2

公开(公告)日：2016-10-18

申请号：US14409776

申请日：2012-06-25

申请人： Shinji Koike ,  Kazuya Mayumi ,  Satoshi Kobayashi

发明人： Shinji Koike ,  Kazuya Mayumi ,  Satoshi Kobayashi

IPC分类号： B23Q1/01 ,  B23C1/027 ,  B23Q1/70 ,  B23Q11/00

CPC分类号： B23Q1/015 ,  B23C1/027 ,  B23C2230/00 ,  B23Q1/017 ,  B23Q1/70 ,  B23Q11/0042 ,  B23Q11/0053 ,  B23Q11/0067 ,  Y02P70/171 ,  Y10T409/30392 ,  Y10T409/304088

摘要： A machine tool includes: a bed, the upper surface of which has the table provided thereon; a cut debris duct which is provided so as to extend rearward from a cut debris discharge opening open at the center, in the left-right direction, of the rear face of the bed, and which discharges cut debris from within the bed to outside of the machine tool; a bifurcated vertically movable body which vertically moves along a pair of vertical guides, and which straddles the cut debris duct, the pair of vertical guides vertically extending on the rear face of the bed at positions on both the left and right sides of the cut debris duct; and a pair of left and right feed screws which extend parallel to the vertical guides, and which move the vertically movable body along the vertical guides.

摘要翻译： 一种机床包括：床，其上表面设置有桌子; 切割的碎屑管被设置成从床的后表面的中心的左右方向上的切割碎屑排出口向后延伸，并且将切碎的碎屑从床内排出到 机床; 一个分叉的可垂直移动的主体，其沿着一对垂直引导件垂直移动，并且跨越切割的碎屑管道，一对垂直引导件在切割碎片的左侧和右侧的位置处垂直延伸在床的后表面上 管; 以及一对平行于垂直导向件延伸的左右进给螺钉，并使垂直移动体沿垂直导向件移动。

公开(公告)号：US08846779B2

公开(公告)日：2014-09-30

申请号：US12921957

申请日：2009-05-15

申请人： Katsuyuki Kito ,  Masayuki Oya ,  Satoshi Kobayashi

发明人： Katsuyuki Kito ,  Masayuki Oya ,  Satoshi Kobayashi

IPC分类号： C08F2/50 ,  C09D11/00 ,  C08J3/28 ,  C09D11/101 ,  C09D11/38

CPC分类号： C09D11/101 ,  C09D11/38 ,  Y10S522/909

摘要： The present invention provides an energy ray-curable ink composition excellent in the continuous discharge property, and excellent in curability and adherability. The present invention relates to an energy ray-curable ink composition which contains a coloring agent, contains only a monofunctional monomer having an acrylic equivalent of 300 or less, and having one ethylenic double bond in one molecule, and a polyfunctional monomer having an acrylic equivalent of 150 or less, and having two or more ethylenic double bonds in one molecule as a polymerizable compound, contains an α-aminoalkylphenone compound and a thioxanthone compound as a photopolymerization initiator, and contains a silicone compound having a polydimethylsiloxane structure as a surface conditioner.

摘要翻译： 本发明提供了连续放电性优异，固化性和粘接性优异的能量射线固化性油墨组合物。 本发明涉及一种含有着色剂的能量射线固化性油墨组合物，其仅含有丙烯酸当量为300以下，单分子中具有1个烯属双键的单官能单体和具有丙烯酸当量的多官能单体 150以下，在1分子中具有2个以上的烯属双键作为聚合性化合物，含有α-氨基烷基苯酮化合物和噻吨酮化合物作为光聚合引发剂，并含有作为表面调节剂的聚二甲基硅氧烷结构的硅氧烷化合物。

公开(公告)号：US08633485B2

公开(公告)日：2014-01-21

申请号：US13075436

申请日：2011-03-30

申请人： Satoshi Kobayashi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Daisuke Kawae

发明人： Satoshi Kobayashi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Daisuke Kawae

IPC分类号： H01L31/00 ,  H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L21/02

CPC分类号： H01L29/41733 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region.

摘要翻译： 提供具有高电特性和优异可靠性的薄膜晶体管的显示装置及其制造方法。 栅电极，设置在栅电极上的栅极绝缘膜，设置在栅绝缘膜上并具有微晶半导体的第一半导体层，设置在第一半导体层上并具有非晶半导体的第二半导体层，以及源极区 并且设置在第二半导体层上的漏极区。 第一半导体层具有比第二半导体层高的结晶度。 第二半导体层包括具有不同于源极区域的导电类型和源极区域与漏极区域之间的漏极区域的导电类型的杂质区域。

公开(公告)号：US08378340B2

公开(公告)日：2013-02-19

申请号：US13487405

申请日：2012-06-04

申请人： Satoshi Kobayashi ,  Satoshi Mikami

发明人： Satoshi Kobayashi ,  Satoshi Mikami

IPC分类号： H01L35/24 ,  C07D333/76

CPC分类号： C07D307/91

摘要： An aromatic compound of the following formula (1), (2), (5) or (6), wherein, Ar1 and Ar3 represent a tetra-valent aromatic hydrocarbon group or a tetra-valent heterocyclic group, and Ar2, Ar4, Ar5, Ar6 and Ar7 represent a tri-valent aromatic hydrocarbon group or a tri-valent heterocyclic group, A1 represents —Z1—, —Z2—Z3— or —Z4═Z5—, wherein Z1, Z2 and Z3 represent O, S or the like and Z4 and Z5 represent N, B, P or the like, X1, X2, X3, X4, X9, X10, X11, and X12 represent a halogen atom or the like.

摘要翻译： 下式（1），（2），（5）或（6）的芳族化合物，其中Ar1和Ar3表示四元芳香族烃基或四价杂环基，Ar2，Ar4，Ar5 中，Ar 6和Ar 7表示3价芳香族烃基或3价杂环基，A1表示-Z 1 - ，Z 2 -Z 3 - 或-Z 4 = Z 5 - ，其中Z 1，Z 2和Z 3表示O，S或 Z 4和Z 5表示N，B，P等，X 1，X 2，X 3，X 4，X 9，X 10，X 11和X 12表示卤素原子等。