公开(公告)号：US09881882B2

公开(公告)日：2018-01-30

申请号：US15335226

申请日：2016-10-26

Applicant: MEDIATEK INC.

Inventor： Chih-Chun Hsu ,  Sheng-Mou Lin

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.

公开(公告)号：US20240079787A1

公开(公告)日：2024-03-07

申请号：US18233335

申请日：2023-08-14

Applicant: MEDIATEK INC.

Inventor： Debapratim Dhara ,  Shih-Chia Chiu ,  Yen-Ju Lu ,  Sheng-Mou Lin

IPC: H01Q9/04 ,  H01Q1/48

CPC classification number: H01Q9/045 ,  H01Q1/48

Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.

公开(公告)号：US20240038443A1

公开(公告)日：2024-02-01

申请号：US18218003

申请日：2023-07-03

Applicant: MEDIATEK INC.

Inventor： Hsin-Yu Hung ,  Ruey-Bo Sun ,  Sheng-Mou Lin

IPC: H01F27/34 ,  H01F27/29 ,  H01F27/28

CPC classification number: H01F27/34 ,  H01F27/29 ,  H01F27/2804

Abstract: A semiconductor device includes a substrate; a first terminal and a second terminal; and a conductor arranged on the substrate between the first terminal and the second terminal to constitute an inductor shaped for forming a first loop and a second loop arranged side-by-side along a first direction. A crossing of the conductor with itself is present between the first loop and the second loop. The first loop and the second loop define a first enclosed area and a second enclosed area, respectively. At least one ground bar traverses either the first loop or the second loop.

公开(公告)号：US10910323B2

公开(公告)日：2021-02-02

申请号：US16535019

申请日：2019-08-07

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou Lin ,  Wen-Chou Wu ,  Hsing-Chih Liu

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18

Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

公开(公告)号：US10679949B2

公开(公告)日：2020-06-09

申请号：US15411077

申请日：2017-01-20

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou Lin ,  Duen-Yi Ho

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/528

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.

公开(公告)号：US20200051925A1

公开(公告)日：2020-02-13

申请号：US16526632

申请日：2019-07-30

Applicant: MediaTek Inc.

Inventor： Yi-Chieh Lin ,  Sheng-Mou Lin ,  Wen-Chou Wu

IPC: H01L23/552 ,  H01L23/498 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02

Abstract: A semiconductor device includes a first layer structure, a first layer structure, a second layer structure and a passive electronic component. The second layer structure is disposed below the first layer structure and coupled to a ground. The conductive structure is coupled to the first layer structure. The conductive structure is installed vertically between the first layer structure and the second layer structure, and is coupled to a first pad of the second layer structure. The passive electronic component comprises a first terminal coupled to the first pad of the second layer structure and a second terminal coupled to a second pad of the second layer structure. The conductive structure and the passive electronic component are connected in series between the first layer structure and the ground to form a conductive path for conducting at least one electromagnetic interference signal to the ground.

公开(公告)号：US20180122747A1

公开(公告)日：2018-05-03

申请号：US15794128

申请日：2017-10-26

Applicant: MEDIATEK INC.

Inventor： Ruey-Bo Sun ,  Sheng-Mou Lin ,  Wen-Chou Wu

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/522 ,  H01L49/02 ,  H01L23/495

CPC classification number: H01L23/552 ,  H01L23/4951 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L25/16 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate, a semiconductor die, a base and a first inductor structure. The substrate has a die-attach surface and a solder-ball-attach surface opposite to the die-attach surface. The semiconductor die is mounted on the die-attach surface of the substrate. The semiconductor die includes a radio-frequency (RF) circuit and a first RF die pad electrically connected to the RF circuit. The base is mounted on the solder-ball-attach surface of the substrate. The first inductor structure is positioned on the substrate, the semiconductor die or the base. The first inductor structure includes a first terminal electrically connected to the first die pad and a second terminal electrically connected to a ground terminal.