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公开(公告)号：US09984144B2
公开(公告)日：2018-05-29
申请号：US14827373
申请日：2015-08-17
发明人： Gil Levy , Pedro Reviriego , Salvatore Pontarelli
CPC分类号： G06F17/30598
摘要： A method for classification includes extracting respective classification keys from a collection of data items and receiving a corpus of rules for matching to the classification keys. At least some of the rules include masked bits in addition to the unmasked bits. Rule patterns are extracted from the corpus, defining different, respective sequences of masked and unmasked bits to which one or more of the rules conform. The rule patterns are grouped into extended rule patterns, such that the respective set of unmasked bits in any rule pattern is a superset of the unmasked bits in the extended rule pattern into which it is grouped. Rule entries corresponding to the rules are computed using the extended rule patterns and are stored in a random access memory (RAM). The data items are classified by matching the respective classification keys to the rule entries in the RAM.
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公开(公告)号：US09892057B2
公开(公告)日：2018-02-13
申请号：US15086095
申请日：2016-03-31
发明人： Gil Levy , Salvatore Pontarelli , Pedro Reviriego
IPC分类号： G06F12/10 , G06F12/1018 , G06F12/02 , G06F12/04 , G06F17/30 , H04L12/743
CPC分类号： G06F12/1018 , G06F12/0292 , G06F12/04 , G06F17/3033 , H04L45/7453 , H04L45/7457
摘要： In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.
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公开(公告)号：US11502912B2
公开(公告)日：2022-11-15
申请号：US17137729
申请日：2020-12-30
发明人： Gil Levy , Pedro Reviriego , Salvatore Pontarelli
摘要： A network device includes at least one communication ingress port, ingress packet processing circuitry and a packet-action cache memory (PACM). The at least one communication ingress port is configured to receive packets including packet headers from a network. The ingress packet processing circuitry is configured to receive the packets and to process the packets in accordance with respective packet actions specified for the packets. The PACM is configured to store one or more of the packet actions in association with one or more respective fingerprints which are calculated over the packet headers of the corresponding packets, for use by the ingress packet processing circuitry. The fingerprints are smaller than the corresponding packet headers.
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公开(公告)号：US11327974B2
公开(公告)日：2022-05-10
申请号：US16052646
申请日：2018-08-02
发明人： Gil Levy , Aviv Kfir , Salvatore Pontarelli , Pedro Reviriego , Matty Kadosh
IPC分类号： G06F16/2455 , G06F16/28
摘要： A collection of rules comprising fields that may have wildcard values. The method includes defining first and second subsets of the fields, the second subset being exclusive of the first subset. Intersections of overlapping fields of the first subset are added to the first subset to form an augmented first subset. Metadata from the augmented first subset and the fields not selected for the first subset are combined to define second parts of the rules. Data items are classified by matching a search key to one of the first parts and one of the second parts of the rules.
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公开(公告)号：US20190294549A1
公开(公告)日：2019-09-26
申请号：US15925815
申请日：2018-03-20
发明人： Gil Levy , Aviv Kfir , Salvatore Pontarelli , Pedro Reviriego
IPC分类号： G06F12/0864 , H04L12/747 , H04L12/745 , H04L12/743
摘要： A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A hash function is applied to the masked destination address to access a hash table. When the number of most significant bits corresponding to the value in the hash table in one of the cache entries and in the destination address are identical, routing information for the packet is retrieved from the cache entry.
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公开(公告)号：US20170068669A1
公开(公告)日：2017-03-09
申请号：US14846777
申请日：2015-09-06
发明人： Gil Levy , Pedro Reviriego , Salvatore Pontarelli
IPC分类号： G06F17/30
CPC分类号： G06F17/3033 , H04L45/7453
摘要： Decision apparatus includes a first memory bank, containing a first table of hash composition factors, and a second memory bank, containing second and third tables of associative entries. A logic pipeline receives a sequence of data items and extracts a search key from each data item. A pre-hash circuit computes a first index by applying a first hash function to the search key. A first lookup circuit reads a hash composition factor from a location in the first memory bank indicated by the first index, and a hash circuit compute second and third indices as different combinations, determined by the hash composition factor, of second and third hash functions applied by the hash circuit to the search key. A second lookup circuit reads the entries in the second and third tables that are indicated respectively by the second and third indices.
摘要翻译： 决策装置包括第一存储体，其包含散列组合因子的第一表和包含第二和第三表的关联项的第二存储体。 逻辑流水线接收数据项序列，并从每个数据项提取搜索关键字。 预散列电路通过对搜索关键字应用第一散列函数来计算第一索引。 第一查找电路从由第一索引指示的第一存储体中的位置读取散列构成因子，并且散列电路计算第二和第三索引作为由哈希构成因子确定的应用的第二和第三散列函数应用的不同组合 通过哈希电路到搜索键。 第二查找电路读取由第二和第三索引分别指示的第二和第三表中的条目。
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公开(公告)号：US11782895B2
公开(公告)日：2023-10-10
申请号：US17013697
申请日：2020-09-07
发明人： Aviad Levy , Gil Levy , Pedro Reviriego , Salvatore Pontarelli
CPC分类号： G06F16/2255 , G06F1/12
摘要： A hashing apparatus includes a memory and circuitry. The memory stores (i) multiple hash tables storing associative entries, each including at least one entry key and a respective value, the hash tables are associated with respective different hash functions, and an associative entry is accessible by applying the relevant hash function to a key matching an entry key in the associative entry, and (ii) an affinity table that stores table-selectors for selecting hash tables with which to start a key lookup. The circuitry receives a key, reads from the affinity table, by applying an affinity function to the key, a table-selector that selects a hash table, accesses in the selected hash table an associative entry by applying the hash function associated with the selected hash table to the key, and in response to detecting that the key matches an entry key in the associative entry, outputs the respective value.
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公开(公告)号：US11550715B2
公开(公告)日：2023-01-10
申请号：US16994600
申请日：2020-08-16
发明人： Gil Levy , Pedro Reviriego , Salvatore Pontarelli
摘要： A system includes a memory, including a plurality of memory locations having different respective addresses, and a processor. The processor is configured to compute one of the addresses from (i) a first sequence of bits derived from a tag of a data item, and (ii) a second sequence of bits representing a class of the data item. The processor is further configured to write the data item to the memory location having the computed address and/or read the data item from the memory location having the computed address. Other embodiments are also described.
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公开(公告)号：US11502957B2
公开(公告)日：2022-11-15
申请号：US17224208
申请日：2021-04-07
发明人： Gil Levy , Aviv Kfir , Matty Kadosh , Salvatore Pontarelli , Pedro Reviriego
IPC分类号： H04L45/748 , H04L45/02 , H04L45/00 , H04L45/42 , H04L45/7453 , H04L45/48
摘要： In one embodiment, a packet processing apparatus includes interfaces, a memory to store a representation of a routing table as a binary search tree of address prefixes, and store a marker with an embedded prefix including k marker bits providing a marker for an address prefix of a node corresponding to a prefix length greater than k, and n additional bits, such that the k marker bits concatenated with the n additional bits provide another address prefix, packet processing circuitry configured upon receiving a data packet having a destination address, to traverse the binary search tree to find a longest prefix match, compare a key with the k marker bits, extract an additional n bits from the destination address, and compare the extracted n bits with the n additional bits, and process the data packet in accordance with a forwarding action indicated by the longest prefix match.
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公开(公告)号：US20220210022A1
公开(公告)日：2022-06-30
申请号：US17137729
申请日：2020-12-30
发明人： Gil Levy , Pedro Reviriego , Salvatore Pontarelli
摘要： A network device includes at least one communication ingress port, ingress packet processing circuitry and a packet-action cache memory (PACM). The at least one communication ingress port is configured to receive packets including packet headers from a network. The ingress packet processing circuitry is configured to receive the packets and to process the packets in accordance with respective packet actions specified for the packets. The PACM is configured to store one or more of the packet actions in association with one or more respective fingerprints which are calculated over the packet headers of the corresponding packets, for use by the ingress packet processing circuitry. The fingerprints are smaller than the corresponding packet headers.
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