METHOD, SYSTEM, AND CIRCUIT WITH A DRIVER OUTPUT INTERFACE HAVING A COMMON MODE CONNECTION COUPLED TO A TRANSISTOR BULK CONNECTION
    11.
    发明申请
    METHOD, SYSTEM, AND CIRCUIT WITH A DRIVER OUTPUT INTERFACE HAVING A COMMON MODE CONNECTION COUPLED TO A TRANSISTOR BULK CONNECTION 有权
    具有连接到晶体管大容量连接的共模连接的驱动器输出接口的方法,系统和电路

    公开(公告)号:US20130120028A1

    公开(公告)日:2013-05-16

    申请号:US13294928

    申请日:2011-11-11

    IPC分类号: H03K3/00 G06F19/00

    摘要: A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

    摘要翻译: 具有共模连接的多端子输出包括具有第一端子和第二端子的输出端,并且在第一端子和第二端子之间具有共模连接。 晶体管的体连接耦合到共模连接。 产生第一组控制信号和第二组控制信号。 第一组控制信号中的每一个具有与第一功率域相关联的第一导轨电压电平。 第二组控制信号是从第一组控制信号产生的。 第二组控制信号中的每一个具有与第二功率域相关联的第二轨电压电平。 第二功率域与输出驱动器的输出的共模电压相关联。

    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK
    12.
    发明申请
    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK 有权
    高速数据测试无高速位时钟

    公开(公告)号:US20130030767A1

    公开(公告)日:2013-01-31

    申请号:US13189926

    申请日:2011-07-25

    IPC分类号: G06F11/30

    摘要: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式,其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样,以产生采样的第一高速数据路径,然后以低速基准时钟的速度进行测试。

    SYSTEMS AND METHODS FOR CONTROLLING BRIGHTNESS OF COLD-CATHODE FLUORESCENT LAMPS WITH WIDE DIMMING RANGE AND ADJUSTABLE MINIMUM BRIGHTNESS
    13.
    发明申请
    SYSTEMS AND METHODS FOR CONTROLLING BRIGHTNESS OF COLD-CATHODE FLUORESCENT LAMPS WITH WIDE DIMMING RANGE AND ADJUSTABLE MINIMUM BRIGHTNESS 有权
    用于控制具有宽度调节范围和可调光最小亮度的冷阴极荧光灯亮度的系统和方法

    公开(公告)号:US20110316428A1

    公开(公告)日:2011-12-29

    申请号:US12861137

    申请日:2010-08-23

    IPC分类号: H05B37/02

    摘要: System and method for adjusting brightness of one or more cold-cathode fluorescent lamps. The system includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level.

    摘要翻译: 用于调节一个或多个冷阴极荧光灯的亮度的系统和方法。 该系统包括被配置为接收调光电压和第一阈值电压并产生输出电压的电压选择器。 输出电压从由调光电压和第一阈值电压组成的组中选择。 另外,该系统包括耦合到第一电容器并被配置为产生与第一电容器的斜坡信号的振荡器,以及被配置为接收斜坡信号和输出电压并产生第一信号的信号发生器。 第一个信号对应于灯的亮度级别。 此外,该系统包括配置成接收第一信号并输出​​第二信号的亮度检测器。 第二信号指示灯亮度是否高于阈值亮度级。

    Ether Compounds with Nitrogen-Containing 5-Member Heterocycle and Uses Thereof
    14.
    发明申请
    Ether Compounds with Nitrogen-Containing 5-Member Heterocycle and Uses Thereof 有权
    具有含氮5元杂环的醚化合物及其用途

    公开(公告)号:US20110178149A1

    公开(公告)日:2011-07-21

    申请号:US13121334

    申请日:2009-11-25

    摘要: The invention relates to ether compounds with nitrogen-containing 5-member heterocycle, represented by formula (I): The groups are as defined as specification.The compounds of the present invention have broad-spectrum insecticidal activities, and they are very effective to lepidopterous pests, including Ostrinia nubilalis, sugarcane borer, summer fruit tortrix moth, Grapholitha inopinata, Lymantria dispar, Cnaphalocrocis medialis, Pyrausta nubilalis, Heliothis assulta, Grapholitha molesta, Plutella xylostella, Laphygma exigua, Prodenialitura and the like, especially more effective to Plutella xylostella and Laphygma exigua, and can have very good effects at very low doses. And the compounds of present invention have high activities to homopteran pests such as aphid. At the same time, some compounds of present invention have very good fungicidal activities, and can be used for preventing wheat powdery mildew, cucumber downy mildew, vegetable grey mould and the like.

    摘要翻译: 本发明涉及具有式(I)表示的含氮的5-元杂环的醚化合物:这些基团如规定所定义。 本发明化合物具有广谱杀虫活性,对鳞翅目害虫非常有效,其中包括鸵鸟,甘蔗螟,夏季果蝇蛾,,,ata disp disp disp disp,,is is,,,a a a a a a a a a a a a a a a a a a a a 禾本小菜,小菜蛾,小菜蛾等,对小菜蛾和小菜蛾特别有效,在非常低的剂量下具有非常好的效果。 本发明化合物对同翅目害虫如蚜虫具有高活性。 同时,本发明的一些化合物具有非常好的杀真菌活性,可用于预防小麦白粉病,黄瓜霜霉病,植物灰霉病等。

    Method, system, and circuit with a driver output interface having a common mode connection coupled to a transistor bulk connection
    16.
    发明授权
    Method, system, and circuit with a driver output interface having a common mode connection coupled to a transistor bulk connection 有权
    具有驱动器输出接口的方法,系统和电路具有耦合到晶体管体连接的共模连接

    公开(公告)号:US08890601B2

    公开(公告)日:2014-11-18

    申请号:US13294928

    申请日:2011-11-11

    摘要: A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

    摘要翻译: 具有共模连接的多端子输出包括具有第一端子和第二端子的输出端,并且在第一端子和第二端子之间具有共模连接。 晶体管的体连接耦合到共模连接。 产生第一组控制信号和第二组控制信号。 第一组控制信号中的每一个具有与第一功率域相关联的第一导轨电压电平。 第二组控制信号是从第一组控制信号产生的。 第二组控制信号中的每一个具有与第二功率域相关联的第二轨电压电平。 第二功率域与输出驱动器的输出的共模电压相关联。

    Systems and methods for intelligent control of cold-cathode fluorescent lamps
    17.
    发明授权
    Systems and methods for intelligent control of cold-cathode fluorescent lamps 有权
    冷阴极荧光灯智能控制系统和方法

    公开(公告)号:US08598806B2

    公开(公告)日:2013-12-03

    申请号:US13335092

    申请日:2011-12-22

    IPC分类号: H05B41/36

    CPC分类号: H05B41/282

    摘要: System and method for driving one or more cold-cathode fluorescent lamps. For example, the method includes generating at least one drive signal associated with a signal frequency, the signal frequency being equal to a first predetermined frequency, receiving a current-sensing signal, the current-sensing signal being associated with a lamp current for the one or more cold-cathode fluorescent lamps in response to at least the first predetermined frequency, and determining whether the current-sensing signal is larger than a first threshold in magnitude, the current-sensing signal being related to the first predetermined frequency. Additionally, the method includes, if the current-sensing signal related to the first predetermined frequency is determined to be larger than the first threshold in magnitude at anytime during a first period of time, changing the signal frequency from the first predetermined frequency to a second predetermined frequency, the second predetermined frequency being different from the first predetermined frequency.

    摘要翻译: 用于驱动一个或多个冷阴极荧光灯的系统和方法。 例如,该方法包括产生与信号频率相关联的至少一个驱动信号,信号频率等于第一预定频率,接收电流感测信号,该电流感测信号与一个灯电流相关联 或更多个冷阴极荧光灯,并且确定电流感测信号是否大于第一阈值,电流感测信号与第一预定频率相关。 另外,如果在第一时间段内的任何时间将与第一预定频率相关的电流感测信号的幅度确定为大于第一阈值,则将该信号频率从第一预定频率改变为第二阈值 预定频率,第二预定频率不同于第一预定频率。

    PARENT-CHILD INTERACTIVE EDUCATION SYSTEM AND METHOD
    18.
    发明申请
    PARENT-CHILD INTERACTIVE EDUCATION SYSTEM AND METHOD 审中-公开
    父母互动教育制度与方法

    公开(公告)号:US20130149686A1

    公开(公告)日:2013-06-13

    申请号:US13818965

    申请日:2011-08-25

    IPC分类号: G09B5/06

    CPC分类号: G09B5/06 G09B7/02 G09B19/00

    摘要: A system comprises a finding scene constructing module, for constructing and displaying a finding scene according to a scene of different levels of difficulty, a base map matching the scene and a target to be found; a finding position processing module, for acquiring a finding position and comparing the finding position with a distribution area of the target to be found, to obtain a comparison result and judge, according to the comparison result, whether a child accurately finds the target to be found; a scoring module, for scoring according to the comparison result, counting total scores and submitting the total scores to a database for storage; an audio and video module, for providing prompts and knowledge for the child according to the comparison result; and a scene element database, for storing the scene of different levels of difficulty, the base map matching the scene, the target, and the audio and video.

    摘要翻译: 一种系统,包括:寻找场景构建模块,用于根据不同难度等级的场景构建和显示寻找场景;匹配场景的基准地图;以及要找到的目标; 查找位置处理模块,用于获取查找位置并将找到位置与要发现的目标的分布区域进行比较,以获得比较结果,并根据比较结果判断一个孩子是否准确地找到目标为 发现 一个评分模块,根据比较结果得分,计算总分数,并将总分数提交到数据库进行存储; 音视频模块,用于根据比较结果为孩子提供提示和知识; 以及用于存储不同难度级别的场景的场景元素数据库,与场景,目标和音频和视频匹配的基本映射。

    HIGH-SPEED PRE-DRIVER AND VOLTAGE LEVEL CONVERTER WITH BUILT-IN DE-EMPHASIS FOR HDMI TRANSMIT APPLICATIONS
    19.
    发明申请
    HIGH-SPEED PRE-DRIVER AND VOLTAGE LEVEL CONVERTER WITH BUILT-IN DE-EMPHASIS FOR HDMI TRANSMIT APPLICATIONS 有权
    高速预驱动器和电压电平转换器,用于HDMI发送应用的内置去差

    公开(公告)号:US20130120029A1

    公开(公告)日:2013-05-16

    申请号:US13294273

    申请日:2011-11-11

    IPC分类号: H03K3/00

    摘要: In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.

    摘要翻译: 在一个例子中,提供了一个高速预驱动器和电压电平转换器,内置去加重HDMI传输应用。 示例性集成电路包括串行器,耦合以从串行器接收差分输入的预驱动器和驱动器。 预驱动器包括全部p型金属氧化物硅(PMOS)交叉耦合电平转换器,其包括四个PMOS晶体管和两个去加重PMOS晶体管,其形成耦合到交叉耦合电平的输出的去加重抽头 转换器。 驱动器耦合到预驱动器输出,并被配置为从前驱动器接收差分输入。

    Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers
    20.
    发明申请
    Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers 有权
    在差分电压模式驱动器中实现对称单端终止的装置

    公开(公告)号:US20130082744A1

    公开(公告)日:2013-04-04

    申请号:US13248485

    申请日:2011-09-29

    IPC分类号: H03K3/00

    CPC分类号: H04L25/0274 H04L25/0278

    摘要: A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

    摘要翻译: 用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。 差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。 独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。 输出驱动器副本控制输出驱动器电路的预定终止阻抗。