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公开(公告)号：US07003432B2
公开(公告)日：2006-02-21
申请号：US10749460
申请日：2003-12-30
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5604
摘要： A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.
摘要翻译： 公开了一种分析存储器件的单元的方法。 通常，生成多个故障签名，其中每个故障签名与一种故障相关联。 根据多个测试图案的电压被施加到存储器件的单元的节点。 然后分析多个模式的单元的失败数据，并且确定单元的失败签名。 然后确定基于多个失败签名的小区的一种故障。 还公开了一种用于分析存储器件单元的系统。 该系统通常包括向存储器件的单元施加不同电压的多个探针。 控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。 最后，输出设备生成指示单元故障类型的输出。
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公开(公告)号：US06720598B1
公开(公告)日：2004-04-13
申请号：US10065124
申请日：2002-09-19
申请人： Joerg Wohlfahrt
发明人： Joerg Wohlfahrt
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. The memory cells of the series group are arranged in pairs in which the capacitors of a memory cell pair are stacked one on top of the other. This advantageously allows for larger capacitor arrays without increasing the chip size.
摘要翻译： 公开了具有串联结构的存储器阵列的IC。 串联组的存储单元成对布置，其中存储单元对的电容器一个堆叠在一起。 这有利地允许更大的电容器阵列而不增加芯片尺寸。
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公开(公告)号：US06717431B2
公开(公告)日：2004-04-06
申请号：US10137142
申请日：2002-05-02
申请人： Dieter Rathei , Joerg Wohlfahrt , Luis G. Andrade , Robert Petter , Thomas S. Taylor , Babatunde Ashiru , Mark E. Luzar , Michael B. Sommer , Ulrich K. Zimmermann
发明人： Dieter Rathei , Joerg Wohlfahrt , Luis G. Andrade , Robert Petter , Thomas S. Taylor , Babatunde Ashiru , Mark E. Luzar , Michael B. Sommer , Ulrich K. Zimmermann
IPC分类号： G01R3126
CPC分类号： H01L22/20
摘要： A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.
摘要翻译： 一种计算半导体晶片的屈服损耗的方法，其通过测试序列测试以导出每个晶片的总失败区域计数，半导体晶片具有多个芯片。 该方法包括计算测试序列中的每个测试的失败区域计数，计算每个晶片的测试序列受限产量损失，以及基于绝对值或绝对值的测试序列限制产量损失分配给选定的测试 通过测试序列的测试识别的故障累积次数。 在一些实施例中，核心参数测试数据与测试序列限制产量相关，并进行分析以确定可修复性。
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公开(公告)号：US06482716B1
公开(公告)日：2002-11-19
申请号：US09481769
申请日：2000-01-11
申请人： Joerg Wohlfahrt
发明人： Joerg Wohlfahrt
IPC分类号： H01L2176
CPC分类号： H01L27/10861 , H01L21/76229 , H01L21/763
摘要： A method for forming uniform-depth recesses across areas of different trench density, in accordance with the present invention, includes providing a substrate having trenches formed therein. The substrate includes regions of different trench density. The trenches are filled with a first filler material, and the first filler material is removed from a surface of the substrate. A second filler material is formed over the surface of the substrate such that the depth of the second filler material is substantially uniform across the regions of different trench density. Recesses are formed in the trenches such that the recess depth below the surface of the substrate is substantially uniform across the regions
摘要翻译： 根据本发明，用于在不同沟槽密度的区域上形成均匀深度凹槽的方法包括提供其中形成有沟槽的衬底。 衬底包括不同沟槽密度的区域。 沟槽填充有第一填充材料，并且从衬底的表面去除第一填充材料。 在衬底的表面上形成第二填充材料，使得第二填充材料的深度在不同沟槽密度的区域上基本均匀。 凹槽形成在沟槽中，使得衬底表面下方的凹陷深度在该区域上基本均匀
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公开(公告)号：US20050149285A1
公开(公告)日：2005-07-07
申请号：US10749460
申请日：2003-12-30
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5604
摘要： A method of analyzing cells of a memory device is disclosed. The method generally comprises steps of establishing a plurality of fail signatures, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system preferably comprises a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.
摘要翻译： 公开了一种分析存储器件的单元的方法。 该方法通常包括建立多个失败签名的步骤，其中每个故障签名与一种故障相关联。 根据多个测试图案的电压被施加到存储器件的单元的节点。 然后分析多个模式的单元的失败数据，并且确定单元的失败签名。 然后确定基于多个失败签名的小区的一种故障。 还公开了一种用于分析存储器件单元的系统。 该系统优选地包括对存储器件的单元施加不同电压的多个探针。 控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。 最后，输出设备生成指示单元故障类型的输出。
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公开(公告)号：US06800890B1
公开(公告)日：2004-10-05
申请号：US10248234
申请日：2002-12-30
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/10817 , H01L27/10852 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.
摘要翻译： 公开了具有串联结构的存储器阵列的IC。 串联组的存储单元包括并联耦合到电容器的晶体管。 电容器包括第一和第二副电容器，一个堆叠在另一个之上。 在堆叠中提供具有两个或更多个子电容器的电容器有利地增加电容器的电容而不增加表面积。
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公开(公告)号：US06553521B1
公开(公告)日：2003-04-22
申请号：US09511169
申请日：2000-02-24
申请人： Dieter Rathei , Thomas Giegold , Joerg Wohlfahrt
发明人： Dieter Rathei , Thomas Giegold , Joerg Wohlfahrt
IPC分类号： G11C2900
CPC分类号： G11C29/44
摘要： The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimensions. The method defines a ratio based on variables supplied by production test systems. By comparing a set of characteristics for a specific semiconductor to the ratio to determine the dominant type of failure on the semiconductor chip. The invention is an efficient method of obtaining information regarding the types of failures common on semiconductor chips.
摘要翻译： 本发明包括用于表征半导体故障的方法。 该方法包括确定存储芯片的某些特性的尺寸。 该方法定义了给定尺寸的半导体的一组特性。 该方法基于生产测试系统提供的变量定义一个比率。 通过将特定半导体的一组特性与比率进行比较来确定半导体芯片上的主要故障类型。 本发明是获得关于半导体芯片上常见的故障类型的信息的有效方法。
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18.发明授权Method and apparatus for fast automated failure classification for semiconductor wafers 失效用于半导体晶片快速自动化故障分类的方法和装置公开(公告)号：US06963813B1
公开(公告)日：2005-11-08
申请号：US09660703
申请日：2000-09-13
申请人： Dieter Rathei , Peter Oswald , Thomas Hladschik , Joerg Wohlfahrt
发明人： Dieter Rathei , Peter Oswald , Thomas Hladschik , Joerg Wohlfahrt
CPC分类号： H01L22/20
摘要： A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.
摘要翻译： 根据本发明的用于对半导体晶片上的故障代码的图案进行分类的方法包括：确定晶片上的芯片的失败代码并检查具有故障代码的晶片上的每个芯片的相邻芯片，以确定具有限定数量的故障代码模式 筹码
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公开(公告)号：US06807084B1
公开(公告)日：2004-10-19
申请号：US10418734
申请日：2003-04-17
IPC分类号： G11C1122
摘要： A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.
摘要翻译： 一个FeRAM存储器芯片包括用于存储数据的非易失性二元电容器存储器单元阵列5。 输入引脚接收要存储的数据，以及指示存储单元数组中应存储数据的位置的地址数据。 FeRAM存储器芯片还具有用于识别外部施加的复位信号的复位单元7。 复位单元7在识别到复位信号时启动复位操作，其中存储在存储单元中的数据的至少一部分被设置为预定值。
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