公开(公告)号：US06963813B1

公开(公告)日：2005-11-08

申请号：US09660703

申请日：2000-09-13

申请人： Dieter Rathei ,  Peter Oswald ,  Thomas Hladschik ,  Joerg Wohlfahrt

发明人： Dieter Rathei ,  Peter Oswald ,  Thomas Hladschik ,  Joerg Wohlfahrt

IPC分类号： H01L21/66 ,  G01N37/00 ,  G06F19/00

CPC分类号： H01L22/20

摘要： A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.

摘要翻译： 根据本发明的用于对半导体晶片上的故障代码的图案进行分类的方法包括：确定晶片上的芯片的失败代码并检查具有故障代码的晶片上的每个芯片的相邻芯片，以确定具有限定数量的故障代码模式 筹码

公开(公告)号：US07003432B2

公开(公告)日：2006-02-21

申请号：US10749460

申请日：2003-12-30

申请人： Joerg Wohlfahrt ,  Thomas Hladschik ,  Jens Holzhaeuser ,  Dieter Rathei

发明人： Joerg Wohlfahrt ,  Thomas Hladschik ,  Jens Holzhaeuser ,  Dieter Rathei

IPC分类号： G01R31/00 ,  G06F19/00

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/5604

摘要： A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.

摘要翻译： 公开了一种分析存储器件的单元的方法。 通常，生成多个故障签名，其中每个故障签名与一种故障相关联。 根据多个测试图案的电压被施加到存储器件的单元的节点。 然后分析多个模式的单元的失败数据，并且确定单元的失败签名。 然后确定基于多个失败签名的小区的一种故障。 还公开了一种用于分析存储器件单元的系统。 该系统通常包括向存储器件的单元施加不同电压的多个探针。 控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。 最后，输出设备生成指示单元故障类型的输出。

公开(公告)号：US20050149285A1

公开(公告)日：2005-07-07

申请号：US10749460

申请日：2003-12-30

申请人： Joerg Wohlfahrt ,  Thomas Hladschik ,  Jens Holzhaeuser ,  Dieter Rathei

发明人： Joerg Wohlfahrt ,  Thomas Hladschik ,  Jens Holzhaeuser ,  Dieter Rathei

IPC分类号： G06F19/00 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/5604

摘要： A method of analyzing cells of a memory device is disclosed. The method generally comprises steps of establishing a plurality of fail signatures, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system preferably comprises a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.

摘要翻译： 公开了一种分析存储器件的单元的方法。 该方法通常包括建立多个失败签名的步骤，其中每个故障签名与一种故障相关联。 根据多个测试图案的电压被施加到存储器件的单元的节点。 然后分析多个模式的单元的失败数据，并且确定单元的失败签名。 然后确定基于多个失败签名的小区的一种故障。 还公开了一种用于分析存储器件单元的系统。 该系统优选地包括对存储器件的单元施加不同电压的多个探针。 控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。 最后，输出设备生成指示单元故障类型的输出。

公开(公告)号：US06717431B2

公开(公告)日：2004-04-06

申请号：US10137142

申请日：2002-05-02

申请人： Dieter Rathei ,  Joerg Wohlfahrt ,  Luis G. Andrade ,  Robert Petter ,  Thomas S. Taylor ,  Babatunde Ashiru ,  Mark E. Luzar ,  Michael B. Sommer ,  Ulrich K. Zimmermann

发明人： Dieter Rathei ,  Joerg Wohlfahrt ,  Luis G. Andrade ,  Robert Petter ,  Thomas S. Taylor ,  Babatunde Ashiru ,  Mark E. Luzar ,  Michael B. Sommer ,  Ulrich K. Zimmermann

IPC分类号： G01R3126

CPC分类号： H01L22/20

摘要： A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.

摘要翻译： 一种计算半导体晶片的屈服损耗的方法，其通过测试序列测试以导出每个晶片的总失败区域计数，半导体晶片具有多个芯片。 该方法包括计算测试序列中的每个测试的失败区域计数，计算每个晶片的测试序列受限产量损失，以及基于绝对值或绝对值的测试序列限制产量损失分配给选定的测试 通过测试序列的测试识别的故障累积次数。 在一些实施例中，核心参数测试数据与测试序列限制产量相关，并进行分析以确定可修复性。

公开(公告)号：US06553521B1

公开(公告)日：2003-04-22

申请号：US09511169

申请日：2000-02-24

申请人： Dieter Rathei ,  Thomas Giegold ,  Joerg Wohlfahrt

发明人： Dieter Rathei ,  Thomas Giegold ,  Joerg Wohlfahrt

IPC分类号： G11C2900

CPC分类号： G11C29/44

摘要： The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimensions. The method defines a ratio based on variables supplied by production test systems. By comparing a set of characteristics for a specific semiconductor to the ratio to determine the dominant type of failure on the semiconductor chip. The invention is an efficient method of obtaining information regarding the types of failures common on semiconductor chips.

摘要翻译： 本发明包括用于表征半导体故障的方法。 该方法包括确定存储芯片的某些特性的尺寸。 该方法定义了给定尺寸的半导体的一组特性。 该方法基于生产测试系统提供的变量定义一个比率。 通过将特定半导体的一组特性与比率进行比较来确定半导体芯片上的主要故障类型。 本发明是获得关于半导体芯片上常见的故障类型的信息的有效方法。

公开(公告)号：US20070013398A1

公开(公告)日：2007-01-18

申请号：US11344664

申请日：2006-02-01

申请人： Dieter Rathei

发明人： Dieter Rathei

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314

摘要： A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A measurement closest to the storage percentile is stored.

摘要翻译： 选择参数参数，其具有较高的规格限制和较低的规格限制。 确定存储百分位数。 如果大于上限规格限值的测量值的数量超过比较低规格限值低的测量值的数量，则存储百分位数等于产品产量百分比，并且等于从一个 百分之百，如果小于较低规格限值的测量值的数量超过大于上限规格的测量值的数量。 存储最接近存储百分位数的测量。

公开(公告)号：US07524683B2

公开(公告)日：2009-04-28

申请号：US11443241

申请日：2006-05-30

申请人： Dieter Rathei

发明人： Dieter Rathei

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  G05B23/0232

摘要： A method of monitoring trends in semiconductor processes is provided. Lot values are assigned to each of a set of wafer lots prior to performing semiconductor processes. After at least some of the semiconductor processes, at least some of the wafer lots are tested to generate a set of test data. A degree of scrambling is calculated for the set of wafer lots already tested using the test data: calculating a current scrambling value by subtracting the lot value of a current wafer lot from a maximum lot value of the lot values assigned for the set of wafer lots to yield the current scrambling value; storing the current scrambling value into a set of scrambling values; and determining a current adjusted maximum scrambling value by multiplying a selected multiplier value with a current maximum scrambling value of the set of scrambling values for a selected number of wafer lots.

摘要翻译： 提供了一种监测半导体工艺趋势的方法。 在执行半导体处理之前，批次值分配给一组晶片批次中的每一个。 在至少一些半导体工艺之后，测试至少一些晶圆批次以产生一组测试数据。 针对已经使用测试数据测试的晶片组的集合计算加扰度：通过从为该组晶片批次分配的批次值的最大批次值中减去当前晶片批次的批次值来计算当前加扰值 产生当前扰频值; 将当前加扰值存储到一组加扰值中; 以及通过将所选择的乘数值与所选数量的晶片批次的所述一组加扰值的当前最大扰频值相乘来确定当前调整的最大扰频值。

公开(公告)号：US07587292B2

公开(公告)日：2009-09-08

申请号：US11344664

申请日：2006-02-01

申请人： Dieter Rathei

发明人： Dieter Rathei

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314

摘要： A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A measurement closest to the storage percentile is stored.

摘要翻译： 选择参数参数，其具有较高的规格限制和较低的规格限制。 确定存储百分位数。 如果大于上限规格限值的测量值的数量超过比较低规格限值低的测量值的数量，则存储百分位数等于产品产量百分比，并且等于从一个 百分之百，如果小于较低规格限值的测量值的数量超过大于上限规格的测量值的数量。 存储最接近存储百分位数的测量。

公开(公告)号：US07496478B2

公开(公告)日：2009-02-24

申请号：US11345154

申请日：2006-02-01

申请人： Dieter Rathei

发明人： Dieter Rathei

IPC分类号： G06F19/00 ,  G06F17/40 ,  G05B99/00

CPC分类号： G05B19/41875 ,  G05B2219/37224 ,  Y02P90/22 ,  Y02P90/265

摘要： A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A number of spatial regions on the wafer is designated. A first group of measurements from the set of measurements is obtained for a first spatial region of the spatial regions. A measurement closest to the storage percentile is stored.

摘要翻译： 选择参数参数，其具有较高的规格限制和较低的规格限制。 确定存储百分位数。 如果大于上限规格限值的测量值的数量超过比较低规格限值低的测量值的数量，则存储百分位数等于产品产量百分比，并且等于从一个 百分之百，如果小于较低规格限值的测量值的数量超过大于上限规格的测量值的数量。 指定晶片上的多个空间区域。 对于空间区域的第一空间区域获得来自该组测量的第一组测量。 存储最接近存储百分位数的测量。

公开(公告)号：US20070020782A1

公开(公告)日：2007-01-25

申请号：US11443241

申请日：2006-05-30

申请人： Dieter Rathei

发明人： Dieter Rathei

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  G05B23/0232

摘要： A method of monitoring trends in semiconductor processes is provided. Lot values are assigned to each of a set of wafer lots prior to performing semiconductor processes. After at least some of the semiconductor processes, at least some of the wafer lots are tested to generate a set of test data. A degree of scrambling is calculated for the set of wafer lots already tested using the test data: calculating a current scrambling value by subtracting the lot value of a current wafer lot from a maximum lot value of the lot values assigned for the set of wafer lots to yield the current scrambling value; storing the current scrambling value into a set of scrambling values; and determining a current adjusted maximum scrambling value by multiplying a selected multiplier value with a current maximum scrambling value of the set of scrambling values for a selected number of wafer lots.

摘要翻译： 提供了一种监测半导体工艺趋势的方法。 在执行半导体处理之前，批次值分配给一组晶片批次中的每一个。 在至少一些半导体工艺之后，测试至少一些晶圆批次以产生一组测试数据。 针对已经使用测试数据测试的晶片组的集合计算加扰度：通过从为该组晶片批次分配的批次值的最大批次值中减去当前晶片批次的批次值来计算当前加扰值 产生当前扰频值; 将当前加扰值存储到一组加扰值中; 以及通过将所选择的乘数值与所选数量的晶片批次的所述一组加扰值的当前最大扰频值相乘来确定当前调整的最大扰频值。