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    Accelerated Read, Modify, Write Operations
    11.
    发明公开
    Accelerated Read, Modify, Write Operations 审中-公开

    公开(公告)号：US20230176738A1

    公开(公告)日：2023-06-08

    申请号：US17990013

    申请日：2022-11-18

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

    Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.

    Central Processing Unit With DSP Engine And Enhanced Context Switch Capabilities
    14.
    发明申请
    Central Processing Unit With DSP Engine And Enhanced Context Switch Capabilities 审中-公开
    具有DSP引擎和增强型上下文切换功能的中央处理单元

    公开(公告)号：US20160321075A1

    公开(公告)日：2016-11-03

    申请号：US15141817

    申请日：2016-04-28

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F9/30

    Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.

    Abstract translation: 集成电路装置具有包括数字信号处理（DSP）引擎和多个上下文的第一中央处理单元，每个上下文具有具有多个寄存器和DSP上下文的CPU上下文，其中DSP上下文具有控制位和 多个DSP寄存器，其中在集成电路器件复位之后，将所有DSP上下文的控制位链接在一起，使得写入DSP上下文的控制位的数据被写入所有其它DSP上下文的相应控制位，并且仅 在上下文切换到另一个上下文并修改另一个DSP上下文中的至少一个控制位之后，另一个上下文的控制位从链路中被切断，以形成DSP上下文的独立控制位。

    Vector fetch bus error handling
    15.
    发明授权
    Vector fetch bus error handling 有权

    公开(公告)号：US12001270B2

    公开(公告)日：2024-06-04

    申请号：US18075458

    申请日：2022-12-06

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F11/00 ,  G06F9/30 ,  G06F11/07

    CPC classification number: G06F11/0745 ,  G06F9/30101

    Abstract: A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

    VECTOR FETCH BUS ERROR HANDLING
    16.
    发明公开
    VECTOR FETCH BUS ERROR HANDLING 审中-公开

    公开(公告)号：US20230176937A1

    公开(公告)日：2023-06-08

    申请号：US18075458

    申请日：2022-12-06

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F11/07 ,  G06F9/30

    CPC classification number: G06F11/0745 ,  G06F9/30101

    Abstract: A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

    Configurable Mailbox Data Buffer Apparatus
    18.
    发明申请
    Configurable Mailbox Data Buffer Apparatus 审中-公开
    可配置邮箱数据缓冲设备

    公开(公告)号：US20160371200A1

    公开(公告)日：2016-12-22

    申请号：US15184789

    申请日：2016-06-16

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris

    IPC: G06F13/10 ,  G06F13/20 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/102 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42 ,  G06F15/167

    Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

    Abstract translation: 单片微控制器具有主核和至少一个从核。 主核心由主系统时钟计时，从核心由从系统时钟计时，并且其中每个核心分别与多个外围设备相关联以形成主微控制器和从微控制器。 在主微控制器和从属微控制器之间提供通信接口，其中通信接口具有多个可配置方向性数据寄存器，与流控制逻辑耦合，流控制逻辑可配置为向多个可配置数据寄存器中的每一个分配方向。

    Central Processing Unit With Enhanced Instruction Set
    19.
    发明申请
    Central Processing Unit With Enhanced Instruction Set 审中-公开
    具有增强指令集的中央处理单元

    公开(公告)号：US20160321202A1

    公开(公告)日：2016-11-03

    申请号：US15141823

    申请日：2016-04-29

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

    IPC: G06F13/16 ,  G06F13/40 ,  G06F12/14

    CPC classification number: G06F13/1673 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/3879 ,  G06F12/14 ,  G06F13/4068 ,  G06F2212/1052

    Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

    Abstract translation: 集成电路具有主处理核心，其具有与非易失性存储器耦合的中央处理单元和独立于主处理核心并具有与易失性程序存储器耦合的中央处理单元操作的从属处理核心，其中主中央处理单元 被配置为将程序指令传送到从处理核心的非易失性存储器，并且其中通过在主处理核心的中央处理单元内执行专用指令来执行程序指令的传送。

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