公开(公告)号：US11144203B2

公开(公告)日：2021-10-12

申请号：US16701281

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield

IPC: G06F3/06 ,  G11C7/10

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

公开(公告)号：US20210208890A1

公开(公告)日：2021-07-08

申请号：US17212330

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Richard C. Murphy ,  Glen E. Hush ,  Vijay S. Ramesh ,  Allan Porterfield ,  Anton Korzh

IPC: G06F9/34 ,  G06F3/06 ,  G06F9/24

Abstract: Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.

公开(公告)号：US20210157491A1

公开(公告)日：2021-05-27

申请号：US17169138

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Richard C. Murphy ,  Glen E. Hush ,  Vijay S. Ramesh ,  Allan Porterfield ,  Anton Korzh

IPC: G06F3/06 ,  G06F12/0868 ,  G06F12/02

Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

公开(公告)号：US11625591B2

公开(公告)日：2023-04-11

申请号：US16913361

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield

IPC: G06N3/063 ,  G06N3/08 ,  G06F9/30 ,  G06F9/50 ,  G06N20/00 ,  G06F9/32 ,  G06N3/04 ,  G06N3/082 ,  G06F40/14 ,  G06F12/0815

Abstract: Systems, apparatuses, and methods related to an extended memory neuromorphic component for performing operations in memory are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can further include a communication subsystem coupled to the at least one of the plurality of computing devices and to a neuromorphic component. At least one of the plurality of computing devices can receive a request from a host to perform an operation, receive an indication of data to be access in a memory device to perform the operation, and send an indication to the neuromorphic component to monitor the data to be accessed. The neuromorphic component can intercept data and determine that a portion of the data should be flagged.

公开(公告)号：US11586355B2

公开(公告)日：2023-02-21

申请号：US17479802

申请日：2021-09-20

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield

IPC: G06F3/06 ,  G11C7/10

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

公开(公告)号：US11481317B2

公开(公告)日：2022-10-25

申请号：US16913304

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield ,  Richard D. Maes

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/16 ,  G06F11/10 ,  G06F9/38 ,  G06F7/57 ,  G06F13/42

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

公开(公告)号：US20220059163A1

公开(公告)日：2022-02-24

申请号：US17453136

申请日：2021-11-01

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield

IPC: G11C13/00 ,  G06F9/54 ,  G06F9/30 ,  G06F7/57

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

公开(公告)号：US20220027297A1

公开(公告)日：2022-01-27

申请号：US17450148

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Richard C. Murphy ,  Glen E. Hush ,  Vijay Ramesh ,  Allan Porterfield ,  Anton Korzh

IPC: G06F13/16

Abstract: Systems, apparatuses, and methods related to a computing tile are described. The computing tile may perform operations on received data to extract some of the received data. The computing tile may perform operations without intervening commands. The computing tile may perform operations on data streamed through the computing tile to extract relevant data from data received by the computing tile. In an example, the computing tile is configured to receive a command to initiate an operation to reduce a size of a block of data from a first size to a second size. The computing tile can then receive a block of data from a memory device coupled to the apparatus. The computing tile can then perform an operation on the block of data to extract predetermined data from the block of data to reduce a size of the block of data from a first size to a second size.

公开(公告)号：US11164625B2

公开(公告)日：2021-11-02

申请号：US17109999

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield

IPC: G11C11/24 ,  G11C13/00 ,  G06F9/54 ,  G06F7/57 ,  G06F9/30

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

公开(公告)号：US10983795B2

公开(公告)日：2021-04-20

申请号：US16366774

申请日：2019-03-27

Applicant: Micron Technology, Inc.

Inventor： Richard C. Murphy ,  Glen E. Hush ,  Vijay S. Ramesh ,  Allan Porterfield ,  Anton Korzh

IPC: G06F9/34 ,  G06F3/06 ,  G06F9/24

Abstract: Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.