公开(公告)号：US20190051656A1

公开(公告)日：2019-02-14

申请号：US15675265

申请日：2017-08-11

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Ugo Russo

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20180269227A1

公开(公告)日：2018-09-20

申请号：US15975902

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  G11C16/16 ,  H01L27/1157 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L29/40117

Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. Dielectric constant (k) of the first material is less than 5.0. Sum of bandgap (BG) and electron affinity (chi) of the second material is no greater than 6.7 eV. The k of the second material is at least 5.0. Sum of BG and chi of the third material is less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material.

公开(公告)号：US09978772B1

公开(公告)日：2018-05-22

申请号：US15458572

申请日：2017-03-14

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L29/792 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/16

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/16 ,  H01L21/28282 ,  H01L27/1157

Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. Dielectric constant (k) of the first material is less than 5.0. Sum of bandgap (BG) and electron affinity (chi) of the second material is no greater than 6.7 eV. The k of the second material is at least 5.0. Sum of BG and chi of the third material is less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material.

公开(公告)号：US20220238547A1

公开(公告)日：2022-07-28

申请号：US17158859

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Chris M. Carlson

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US11211399B2

公开(公告)日：2021-12-28

申请号：US16542061

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Chris M. Carlson

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  G11C5/06

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

公开(公告)号：US11177269B2

公开(公告)日：2021-11-16

申请号：US16277311

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20210202521A1

公开(公告)日：2021-07-01

申请号：US17181901

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/51 ,  H01L29/423

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210074856A1

公开(公告)日：2021-03-11

申请号：US17083190

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20210050363A1

公开(公告)日：2021-02-18

申请号：US16542061

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Chris M. Carlson

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/1157

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

公开(公告)号：US20200258980A1

公开(公告)日：2020-08-13

申请号：US16863117

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L29/06 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L21/764

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.