公开(公告)号：US20230395184A1

公开(公告)日：2023-12-07

申请号：US17959191

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/406

CPC classification number: G11C29/52 ,  G11C11/4093 ,  G11C11/40615

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US20230393930A1

公开(公告)日：2023-12-07

申请号：US17831436

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0688 ,  G06F3/0619 ,  G06F3/0659

Abstract: Systems, apparatuses, and methods related to addressing for data and additional data portions are described herein. In an example method, addressing for data and additional data portions can include accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol. The first command can be a compute express link (CXL) protocol compliant command. The example method can further include converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol. The second command can be a DRAM accessible command. The example method can further include accessing a page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the converted address associated with the first command.

公开(公告)号：US11797717B2

公开(公告)日：2023-10-24

申请号：US16765224

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolo Izzo

IPC: G06F21/85 ,  G06F12/02 ,  G06F21/60 ,  G06F21/79 ,  G06F12/14

CPC classification number: G06F21/85 ,  G06F12/0246 ,  G06F12/1408 ,  G06F21/602 ,  G06F21/79

Abstract: The present disclosure relates to apparatuses and methods for memory management. The disclosure further relates to an interface protocol for flash memory devices including at least a memory array and a memory controller coupled to the memory array.
A host device is coupled to the memory device through a communication channel and a hardware and/or software full encryption-decryption scheme is adopted in the communication channel for data, addresses and commands exchanged between the host device and the memory array.

公开(公告)号：US11656983B2

公开(公告)日：2023-05-23

申请号：US17302966

申请日：2021-05-17

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Dionisio Minopoli

IPC: G06F12/02 ,  G06F12/1045 ,  G06F12/0868

CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/7201

Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer read command comprising a physical address of data to be read from a memory device, wherein the physical address is indicated in at least a portion of a translation layer entry previously provided to the host system with a response to a host-resident translation layer write command and stored in a host-resident translation layer mapping table. The processing device further performs a read operation to read the data stored at the physical address from the memory device and sends, to the host system, the data from the physical address of the memory device.

公开(公告)号：US20230153204A1

公开(公告)日：2023-05-18

申请号：US18099800

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0238 ,  G06F11/076 ,  G06F2212/7201

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

公开(公告)号：US20230016520A1

公开(公告)日：2023-01-19

申请号：US17861233

申请日：2022-07-10

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

公开(公告)号：US20220326887A1

公开(公告)日：2022-10-13

申请号：US17657870

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.

公开(公告)号：US11340808B2

公开(公告)日：2022-05-24

申请号：US16890511

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.

公开(公告)号：US20220130461A1

公开(公告)日：2022-04-28

申请号：US17518176

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/32

Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.

公开(公告)号：US11183248B1

公开(公告)日：2021-11-23

申请号：US16942568

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.