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    Oxidative trim
    11.
    发明授权
    Oxidative trim 有权

    公开(公告)号：US10985239B2

    公开(公告)日：2021-04-20

    申请号：US16543065

    申请日：2019-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Matthew N. Rocklein ,  An-Jen B. Cheng ,  Fredrick D. Fishburn ,  Sevim Korkmaz ,  Paul A. Paduano

    IPC: H01L49/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/02

    Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.

    Devices having a transistor and a capacitor along a common horizontal level, and methods of forming devices
    12.
    发明授权
    Devices having a transistor and a capacitor along a common horizontal level, and methods of forming devices 有权

    公开(公告)号：US10707210B2

    公开(公告)日：2020-07-07

    申请号：US16150714

    申请日：2018-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Fredrick D. Fishburn

    IPC: H01L27/108

    Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.

    Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices
    13.
    发明申请
    Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices 审中-公开

    公开(公告)号：US20190181142A1

    公开(公告)日：2019-06-13

    申请号：US16150714

    申请日：2018-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Fredrick D. Fishburn

    IPC: H01L27/108

    Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.

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