公开(公告)号：US20200274060A1

公开(公告)日：2020-08-27

申请号：US16870137

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US10249819B2

公开(公告)日：2019-04-02

申请号：US14244486

申请日：2014-04-03

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20180123036A1

公开(公告)日：2018-05-03

申请号：US15857873

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1675

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20160172242A1

公开(公告)日：2016-06-16

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US09299663B2

公开(公告)日：2016-03-29

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/04 ,  H01L23/544 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20150333014A1

公开(公告)日：2015-11-19

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。