公开(公告)号：US12237217B2

公开(公告)日：2025-02-25

申请号：US17188734

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/538

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

公开(公告)号：US10665782B2

公开(公告)日：2020-05-26

申请号：US16110760

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20200274059A1

公开(公告)日：2020-08-27

申请号：US16870108

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US10658580B2

公开(公告)日：2020-05-19

申请号：US15857873

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US09741612B2

公开(公告)日：2017-08-22

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L23/544 ,  H01L21/683 ,  H01L23/48 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US20150145146A1

公开(公告)日：2015-05-28

申请号：US14612926

申请日：2015-02-03

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76865 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5384 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

Abstract translation: 暴露半导体器件的导电通路的方法可包括将阻挡材料定位在从衬底的背面延伸至至少基本上符合导电通孔的导电通孔上。 自平面化隔离材料可以位于与衬底相对的阻挡材料的一侧上。 自平坦化隔离材料的暴露表面可以至少基本上是平面的。 可以去除自平坦化隔离材料的一部分，阻挡材料的一部分和至少一些导电通孔的一部分，以暴露每个导电通孔。 在将阻挡材料的至少一个横向延伸的部分暴露在基底附近之前可以停止移除。

公开(公告)号：US11050020B2

公开(公告)日：2021-06-29

申请号：US16870137

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20210183697A1

公开(公告)日：2021-06-17

申请号：US17188734

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/48

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

公开(公告)号：US20180366645A1

公开(公告)日：2018-12-20

申请号：US16110760

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1675

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20150287916A1

公开(公告)日：2015-10-08

申请号：US14244486

申请日：2014-04-03

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1675

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

Abstract translation: 一种形成半导体结构的方法。 该方法包括在衬底上的至少一部分堆叠结构上形成衬垫的保护部分。 保护部分包括配制成粘附到堆叠结构的材料。 衬垫的保形部分形成在衬垫的保护部分或衬垫的保护部分上以及堆叠结构的暴露的材料上。 保护部分和保形部分中的至少一个不包括铝。 公开了形成半导体结构的附加方法，半导体结构包括包括保护部分和保形部分的衬垫。