公开(公告)号：US20220036939A1

公开(公告)日：2022-02-03

申请号：US16942503

申请日：2020-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

公开(公告)号：US10937473B2

公开(公告)日：2021-03-02

申请号：US16058687

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita

IPC: G11C7/22 ,  G11C7/10

Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.

公开(公告)号：US10803923B2

公开(公告)日：2020-10-13

申请号：US16444365

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/1534 ,  H03K5/05 ,  H03K3/037 ,  H03K5/135 ,  G11C7/22 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US10418081B1

公开(公告)日：2019-09-17

申请号：US16156862

申请日：2018-10-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita ,  Shuichi Murai ,  Kohei Nakamura

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

公开(公告)号：US20230290386A1

公开(公告)日：2023-09-14

申请号：US17692066

申请日：2022-03-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa

IPC: G11C7/08 ,  G11C8/10

CPC classification number: G11C7/08 ,  G11C8/10

Abstract: Apparatuses for controlling power supply to sense amplifiers are described. An example apparatus includes a bank. The bank includes: a first plurality of memory cells; a second plurality of memory cells; first sense amplifiers coupled to the first plurality of memory cells; second sense amplifiers coupled to the second plurality of memory cells; a first power control circuit and a coupled to the first sense amplifiers at a common power supply node; and a second power control circuit coupled to the second sense amplifiers at the common power supply node. The first and second power control circuits receive a plurality of control signals. The first and second power control circuits comprise first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals. The first drive strength and the second drive strength are different from each other.

公开(公告)号：US11462259B2

公开(公告)日：2022-10-04

申请号：US17114338

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/406

Abstract: Apparatuses and methods for controlling internal current are disclosed herein, An example apparatus includes a semiconductor device including a power node. The semiconductor device receives power as an internal current, and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current and provides a second portion of the internal current as an external current at the power node during the first mode. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.

公开(公告)号：US10734046B2

公开(公告)日：2020-08-04

申请号：US16436655

申请日：2019-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita ,  Shuichi Murai ,  Kohei Nakamura

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

公开(公告)号：US10218342B2

公开(公告)日：2019-02-26

申请号：US15636379

申请日：2017-06-28

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: H03K5/04 ,  H03K5/156 ,  H03K5/159

Abstract: Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.

公开(公告)号：US09065456B2

公开(公告)日：2015-06-23

申请号：US14317893

申请日：2014-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroki Takahashi ,  Katsuhiro Kitagawa

IPC: H03L7/06 ,  H03L7/197

CPC classification number: H03L7/1972 ,  H03L7/0814

Abstract: Disclosed herein is a device includes a first delay circuit delaying a first clock signal according to a count value to generate a second clock signal, a phase determination circuit comparing a phase of the first clock signal with a phase of the second clock signal to generate a phase determination signal, an up-down counter updating the count value according to the phase determination signal each time an update signal is activated, and an update control circuit generating the update signal at a variable interval.

Abstract translation: 本文公开了一种装置，包括：第一延迟电路，根据计数值延迟第一时钟信号以产生第二时钟信号;相位确定电路，将第一时钟信号的相位与第二时钟信号的相位进行比较，以产生 相位确定信号，每当激活更新信号时根据相位确定信号更新计数值的升降计数器，以及以可变间隔产生更新信号的更新控制电路。

公开(公告)号：US20220157367A1

公开(公告)日：2022-05-19

申请号：US17590710

申请日：2022-02-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.