公开(公告)号：US11942159B2

公开(公告)日：2024-03-26

申请号：US17591510

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/225 ,  G11C16/32

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

公开(公告)号：US20240062786A1

公开(公告)日：2024-02-22

申请号：US18228148

申请日：2023-07-31

Applicant: Micron Technology, Inc.

Inventor： Kitae Park ,  Aaron Yip

IPC: G11C5/06 ,  H10B80/00 ,  H01L23/528 ,  G11C16/08 ,  H01L25/065

CPC classification number: G11C5/063 ,  H10B80/00 ,  H01L23/5283 ,  G11C16/08 ,  H01L25/0655

Abstract: A memory device includes a memory array die corresponding to a memory array, an access circuitry die corresponding to peripheral circuitry to support access operations with respect to the memory array, and a bonding layer disposed between the memory array die and the access circuitry die to form an interconnection between the memory array and the access circuitry. In some embodiments, the access circuitry die further integrates a local media controller corresponding to the memory array. In some embodiments, the local media controller is located external to the access circuitry die.

公开(公告)号：US20240006007A1

公开(公告)日：2024-01-04

申请号：US17856827

申请日：2022-07-01

Applicant: Micron Technology, Inc.

Inventor： Kitae Park

IPC: G11C29/10 ,  G06F3/06

CPC classification number: G11C29/10 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0673

Abstract: Apparatuses, systems, and methods for predetermined pattern program operations are described according to embodiments of the present disclosure. One example method can include determining a portion of a memory device is invalid and performing a predetermined pattern program operation on the portion of the memory device in response to determining the portion of the memory device is invalid.

公开(公告)号：US20240203508A1

公开(公告)日：2024-06-20

申请号：US18589730

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/225 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.