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公开(公告)号：US20230384353A1
公开(公告)日：2023-11-30
申请号：US17824479
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
CPC classification number: G01R19/0038 , H03K5/14 , G11C7/222 , H03K3/037
Abstract: A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.
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公开(公告)号：US20230289306A1
公开(公告)日：2023-09-14
申请号：US18119576
申请日：2023-03-09
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
CPC classification number: G06F13/30 , G06F13/1668
Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.
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公开(公告)号：US20250105829A1
公开(公告)日：2025-03-27
申请号：US18789278
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Current sensing circuitry and clock management circuitry provide current and clock frequency management. In one example, an apparatus can include a voltage regulator, current sensing circuitry configured to: detect a current associated with the voltage regulator of a system-on-chip (SoC), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to: generate clocking signals for the SoC, select a gradient frequency alteration based on the detected current, and alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.
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公开(公告)号：US20250104794A1
公开(公告)日：2025-03-27
申请号：US18975645
申请日：2024-12-10
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.
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公开(公告)号：US20250103088A1
公开(公告)日：2025-03-27
申请号：US18789228
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F1/06
Abstract: Voltage sensing circuitry and management circuitry provide voltage and clock frequency management. The voltage sensing circuitry may be configured to detect a voltage associated with a system-on-chip (SoC) and determine when the voltage transitions from a first voltage to a second voltage. The management circuitry may be configured to generate clocking signals for the SoC and alter a frequency of the generated clocking signals in response to the detected voltage transition.
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Patent Agency Ranking
公开(公告)号：US12182046B2
公开(公告)日：2024-12-31
申请号：US18119578
申请日：2023-03-09
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.
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公开(公告)号：US20230299754A1
公开(公告)日：2023-09-21
申请号：US17696352
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
IPC: H03K3/037
CPC classification number: H03K3/037
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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公开(公告)号：US20230283386A1
公开(公告)日：2023-09-07
申请号：US17966300
申请日：2022-10-14
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Pranjal Chauhan
Abstract: Clock enable signals are collected and summed. The number of simultaneously enabled clock enable signals can represent switching activity within a system and can be used as an indicator for power management, noise management, etc. of such a system. Digital switching activity sensing include performance of an operation to sum a quantity of open clock gates associated with a plurality of latches that are grouped into multiple subsets of latches. An activity indication is generated based, at least in part, on a result of the operation to sum the quantity of open clock gates associated with the plurality of latches.
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公开(公告)号：US20250165310A1
公开(公告)日：2025-05-22
申请号：US18913696
申请日：2024-10-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F9/50
Abstract: Resource can be managed by accessing, at a resource manager of a system, a leakage-temperature table. The resource manager can determine a dynamic resource pool and a static resource pool of the system based on the leakage-temperature table. The resource manager can receive a resource request from a device of the system. The resource manager can assign resources to the device from the dynamic resource pool and the static resource pool.
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公开(公告)号：US20250165189A1
公开(公告)日：2025-05-22
申请号：US18948878
申请日：2024-11-15
Applicant: Micron Technology, Inc.
Inventor： Leonid Minz
IPC: G06F3/06
Abstract: A method includes receiving a plurality of bit strings to be written to respective memory banks of a memory device, writing a first bit string among the plurality of bit strings to a first rank of a first memory bank among the plurality of memory banks during a first timing period, and writing a second bit string among the plurality of bit strings to a second rank of the first memory bank among the plurality of memory banks during a second timing period.
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