公开(公告)号：US20200266197A1

公开(公告)日：2020-08-20

申请号：US16869316

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US20200098761A1

公开(公告)日：2020-03-26

申请号：US16139816

申请日：2018-09-24

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US20250159889A1

公开(公告)日：2025-05-15

申请号：US19024255

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Damir Fazil ,  Michael E. Koltonski

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10D64/01

Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.

公开(公告)号：US12232317B2

公开(公告)日：2025-02-18

申请号：US17666844

申请日：2022-02-08

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Damir Fazil ,  Michael E. Koltonski

IPC: H10B43/27 ,  H01L21/28 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10

Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.

公开(公告)号：US20240130124A1

公开(公告)日：2024-04-18

申请号：US18324068

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220077176A1

公开(公告)日：2022-03-10

申请号：US17013047

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC: H01L27/11582

Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US10707211B2

公开(公告)日：2020-07-07

申请号：US16139816

申请日：2018-09-24

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/822

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.