公开(公告)号：US10707211B2

公开(公告)日：2020-07-07

申请号：US16139816

申请日：2018-09-24

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/822

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US11296103B2

公开(公告)日：2022-04-05

申请号：US16863000

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Kunal Shrotri ,  Matthew Thorum

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12191249B2

公开(公告)日：2025-01-07

申请号：US17446868

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

IPC: H10B43/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US20230073372A1

公开(公告)日：2023-03-09

申请号：US17446868

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/532

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US10943907B2

公开(公告)日：2021-03-09

申请号：US16869316

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L21/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/822 ,  H01L27/108

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US20200266197A1

公开(公告)日：2020-08-20

申请号：US16869316

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US20200098761A1

公开(公告)日：2020-03-26

申请号：US16139816

申请日：2018-09-24

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US12041779B2

公开(公告)日：2024-07-16

申请号：US17678983

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Kunal Shrotri ,  Matthew Thorum

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220181334A1

公开(公告)日：2022-06-09

申请号：US17678983

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Kunal Shrotri ,  Matthew Thorum

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220005819A1

公开(公告)日：2022-01-06

申请号：US16921641

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Shyam Surthi ,  Matthew Thorum

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The channel-material-string constructions individually comprise a channel-material string that extends through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. The undoped silicon dioxide-comprising strings are etched through the void space in the second tiers left by the etching of the doped silicon dioxide to divide individual of the undoped silicon dioxide-comprising strings into vertically-spaced segments of the undoped silicon dioxide. Structure independent of method is disclosed.