公开(公告)号：US20230380159A1

公开(公告)日：2023-11-23

申请号：US17747126

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Damir Fazil ,  John D. Hopkins ,  Indra V. Chary ,  Tom John ,  Joel D. Peterson ,  Kar Wui Thong ,  Zhaohui Ma

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks that individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material strings directly electrically couples to conductor material of the conductor tier. Individual ones of the channel-material strings in a vertical cross-section comprise an external jog surface that is above the conductor tier and an internal jog surface that is in the conductor tier. Other aspects, including methods, are disclosed.

公开(公告)号：US20230345722A1

公开(公告)日：2023-10-26

申请号：US17726968

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Joshua Wolanyk ,  Richard J. Hill ,  Damir Fazil

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the methods includes forming levels of materials one over another; forming a first opening and a second opening in the levels of materials; forming at least one dielectric material in the first and second openings; forming tiers of materials over the levels of materials and over the dielectric material in the first and second openings; forming a first pillar of a memory cell string, the first pillar extending through the tiers of materials and extending partially into a location of the first opening; and forming a second pillar of a contact structure, the second pillar extending through the tiers of materials and through a location of the second opening.

公开(公告)号：US12232317B2

公开(公告)日：2025-02-18

申请号：US17666844

申请日：2022-02-08

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Damir Fazil ,  Michael E. Koltonski

IPC: H10B43/27 ,  H01L21/28 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10

Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.

公开(公告)号：US20210358951A1

公开(公告)日：2021-11-18

申请号：US17391453

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Justin B. Dorhout ,  Nirup Bandaru ,  Damir Fazil ,  Nancy M. Lomeli ,  Jivaan Kishore Jhothiraman ,  Purnima Narayanan

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210249261A1

公开(公告)日：2021-08-12

申请号：US16789168

申请日：2020-02-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Damir Fazil

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

公开(公告)号：US11706925B2

公开(公告)日：2023-07-18

申请号：US18053134

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Justin B. Dorhout ,  Damir Fazil

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H01L21/311 ,  H01L21/02

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

公开(公告)号：US20230207469A1

公开(公告)日：2023-06-29

申请号：US17582280

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Damir Fazil ,  Indra V. Chary ,  Nancy M. Lomeli ,  Rajasekhar Venigalla

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAV constructions comprise an upper portion directly above and joined with a lower portion. The individual TAV constructions comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method, are disclosed.

公开(公告)号：US11495617B2

公开(公告)日：2022-11-08

申请号：US17032384

申请日：2020-09-25

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Justin B. Dorhout ,  Damir Fazil

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11556

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

公开(公告)号：US11430809B2

公开(公告)日：2022-08-30

申请号：US16984457

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H01L27/11582 ,  G11C5/02 ,  H01L21/768 ,  G11C16/04 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240074179A1

公开(公告)日：2024-02-29

申请号：US17896570

申请日：2022-08-26

Applicant: Micron Technology, Inc

Inventor： John D. Hopkins ,  Damir Fazil ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks. The side interfaces have the conductor material laterally-over opposing sides thereof. Other embodiments, including method, are disclosed.