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公开(公告)号：US20240071435A1
公开(公告)日：2024-02-29
申请号：US18198623
申请日：2023-05-17
Applicant: Micron Technology, Inc.
Inventor： Phong Sy Nguyen , Patrick R. Khayat , Jeffrey S. McNeil , Dung Viet Nguyen , Kishore Kumar Muchherla , James Fitzpatrick
IPC: G11C7/10
CPC classification number: G11C7/1069 , G11C7/1057 , G11C7/106
Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.
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公开(公告)号：US11568937B2
公开(公告)日：2023-01-31
申请号：US17216015
申请日：2021-03-29
Applicant: Micron Technology, Inc.
Inventor： Dung V. Nguyen , Phong Sy Nguyen
Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.
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公开(公告)号：US20220199173A1
公开(公告)日：2022-06-23
申请号：US17127476
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Phong Sy Nguyen , James Fitzpatrick , Kishore Kumar Muchherla
Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.
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公开(公告)号：US20220199172A1
公开(公告)日：2022-06-23
申请号：US17127413
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Phong Sy Nguyen , James Fitzpatrick , Kishore Kumar Muchherla
Abstract: In a coarse programming, the threshold voltage of the memory cell is programmed to a first level representative of N−1 bit values data according to a first mapping between combinations of values of N−1 possible bits and threshold levels. A group identification is representative of whether the first level is an odd or even numbered level in the first mapping. For a fine programming, the memory cell is read, based on the group identification, to obtain the N−1 bit values; and at least one additional bit is received to join the N−1 bit values to form at least N bit values. The threshold voltage of the memory cell is then finely programmed to a second level representative of the at least N bit values according to a second mapping between combinations of values of the at least N possible bits and threshold levels.
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15.发明授权公开(公告)号：US11335407B1
公开(公告)日：2022-05-17
申请号：US17127502
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Phong Sy Nguyen , James Fitzpatrick , Kishore Kumar Muchherla
Abstract: A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.
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Patent Agency Ranking
16.发明授权公开(公告)号：US12277978B2
公开(公告)日：2025-04-15
申请号：US18636901
申请日：2024-04-16
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Phong Sy Nguyen , Dung Viet Nguyen , Sivagnanam Parthasarathy
Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
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公开(公告)号：US20250028447A1
公开(公告)日：2025-01-23
申请号：US18906876
申请日：2024-10-04
Applicant: Micron Technology, Inc.
Inventor： Jeremy Binfet , Violante Moschiano , James Fitzpatrick , Kishore Kumar Muccherla , Jeffrey S. McNeil , Phong Sy Nguyen
IPC: G06F3/06
Abstract: A memory device includes an array of memory cells associated with a plurality of wordlines and control logic operatively coupled with the array of memory cells. The control logic can receive a program command comprising a digital value indicating that a physical address of the program command corresponds to a retired wordline of the plurality of wordlines. The control logic can generate dummy data in response to detecting the digital value within the program command. The memory logic can cause the dummy data to be programmed to memory cells that are selectively coupled to the retired wordline.
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公开(公告)号：US12141437B2
公开(公告)日：2024-11-12
申请号：US17974799
申请日：2022-10-27
Applicant: Micron Technology, Inc.
Inventor： Jeremy Binfet , Violante Moschiano , James Fitzpatrick , Kishore Kumar Muccherla , Jeffrey S. McNeil , Phong Sy Nguyen
IPC: G06F3/06
Abstract: A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.
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公开(公告)号：US20220253354A1
公开(公告)日：2022-08-11
申请号：US17540059
申请日：2021-12-01
Applicant: Micron Technology, Inc.
Inventor： Dung V. Nguyen , Phong Sy Nguyen , Sivagnanam Parthasarathy
Abstract: Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.
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公开(公告)号：US20240412792A1
公开(公告)日：2024-12-12
申请号：US18810198
申请日：2024-08-20
Applicant: Micron Technology, Inc.
Inventor： Phong Sy Nguyen , James Fitzpatrick , Kishore Kumar Muchherla
Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.
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