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1.发明公开公开(公告)号：US20240265979A1
公开(公告)日：2024-08-08
申请号：US18636901
申请日：2024-04-16
CPC分类号： G11C16/3404 , A63B24/0075 , G11C16/26 , A63B2024/0068 , A63B2024/0093 , A63B2220/836 , A63B2230/06
摘要： A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
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2.发明授权公开(公告)号：US11830545B2
公开(公告)日：2023-11-28
申请号：US17124380
申请日：2020-12-16
发明人： Phong Sy Nguyen , James Fitzpatrick
CPC分类号： G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/10 , G11C16/26
摘要： A memory system to generate data with a relation among data groups for reliably storing a predetermined number of bits per memory cell in memory cells. For example, from first groups of date bits, a second group of data bits is generated. Data groups of the predetermined number is formed to have the first groups and the second group and a predetermined relation (e.g., XOR or XNOR) among the data groups. Threshold levels of memory cells in a memory cell group are determined based on a predetermined mapping, where a threshold level of each memory cell is determined to represent one bit from each of the data groups. In the predetermined mapping, bit values represented by any two successive threshold levels differ by one bit. Threshold voltages in the memory cell group are programmed according to the threshold levels to store the data groups with improved reliability.
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公开(公告)号：US12073892B2
公开(公告)日：2024-08-27
申请号：US17940317
申请日：2022-09-08
CPC分类号： G11C16/3404 , G11C7/106 , G11C7/1087 , G11C16/10 , G11C16/26 , G11C16/30
摘要： A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.
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公开(公告)号：US11699491B2
公开(公告)日：2023-07-11
申请号：US17247643
申请日：2020-12-18
CPC分类号： G11C16/20 , G11C16/26 , G11C16/30 , G11C2211/561
摘要： Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.
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公开(公告)号：US11663079B2
公开(公告)日：2023-05-30
申请号：US17540059
申请日：2021-12-01
CPC分类号： G06F11/1076 , G06F11/076 , G06F11/0772 , H03M13/1575
摘要： Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.
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公开(公告)号：US20220246214A1
公开(公告)日：2022-08-04
申请号：US17724940
申请日：2022-04-20
摘要： A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.
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7.发明申请公开(公告)号：US20220199154A1
公开(公告)日：2022-06-23
申请号：US17127459
申请日：2020-12-18
摘要： A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of values of the data bits according to a mapping between combinations of values of bits and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. XOR (or XNOR) is used to combine the data bits into bits of a group identification of a first group, among the plurality of groups, that contains the first level. The memory device reads, using the group identification, the data bits back from the first memory cell to finely program the threshold voltage of the memory cell to represent the data bits.
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公开(公告)号：US20220253354A1
公开(公告)日：2022-08-11
申请号：US17540059
申请日：2021-12-01
摘要： Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.
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公开(公告)号：US11990186B2
公开(公告)日：2024-05-21
申请号：US17724940
申请日：2022-04-20
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/0644 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G11C11/56 , G11C16/26 , G11C16/0483
摘要： A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.
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10.发明授权公开(公告)号：US11984171B2
公开(公告)日：2024-05-14
申请号：US17841096
申请日：2022-06-15
CPC分类号： G11C16/3404 , A63B24/0075 , G11C16/26 , A63B2024/0068 , A63B2024/0093 , A63B2220/836 , A63B2230/06
摘要： A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
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