公开(公告)号：US20240055523A1

公开(公告)日：2024-02-15

申请号：US17883736

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Bingwu Liu ,  Shivani Srivastava ,  Dan Mihai Mocuta

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/0847 ,  H01L27/10897 ,  H01L29/66545 ,  H01L21/823431

Abstract: Electronic devices and methods are disclosed, including transistors with thick gate dielectric layers. Selected devices and methods shown include multiple layer gate dielectrics. Selected devices and methods shown include a gate dielectric with a first layer having a first width, and a second layer over the first layer, wherein the second layer has a second width smaller than the first width.

公开(公告)号：US11811874B2

公开(公告)日：2023-11-07

申请号：US17719790

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Sharmila Velamur ,  Fatma Arzum Simsek-Ege ,  Shivani Srivastava ,  Marsela Pontoh ,  Lavanya Sriram

IPC: H04L67/125 ,  H04L67/00

CPC classification number: H04L67/125 ,  H04L67/34

Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.

公开(公告)号：US20230335582A1

公开(公告)日：2023-10-19

申请号：US17720122

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Toshihiko Miyashita ,  Dan Mihai Mocuta ,  Bingwu Liu ,  Stephen David Snyder

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0642 ,  H01L29/785 ,  H01L27/0886 ,  H01L29/66795

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include semiconductor devices having two or more fins, the fins separated by one or more inter-fin trenches. An isolation structure is included adjacent to the two or more fins, the isolation structure having a depth greater than the inter-fin trench depth.

公开(公告)号：US10991700B2

公开(公告)日：2021-04-27

申请号：US16793888

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308 ,  G11C11/408

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US20200185389A1

公开(公告)日：2020-06-11

申请号：US16793888

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US10593678B1

公开(公告)日：2020-03-17

申请号：US16111499

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308 ,  G11C11/408

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.