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    DIFFERENTIAL SUBTHRESHOLD READ OF MEMORY CELL PAIR IN A MEMORY DEVICE
    11.
    发明公开
    DIFFERENTIAL SUBTHRESHOLD READ OF MEMORY CELL PAIR IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230377646A1

    公开(公告)日：2023-11-23

    申请号：US17748666

    申请日：2022-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Umberto di Vincenzo ,  Michele Maria Venturini

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2013/0042 ,  H03K19/20

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a differential read operation is performed on a memory cell pair. Bitlines or digit lines are used to select the memory cells. The read operation is performed in a subthreshold mode in which the memory cells of the pair do not threshold (e.g., do not switch or snap). A voltage on a wordline used to select the memory cell pair is ramped to increasing magnitudes of voltage while the bitline or digit line voltages are held fixed. One or more detectors are used to determine a difference in leakage currents of the two memory cells. A logic state is determined (e.g., using at least one detector) based on the difference in leakage currents. A feedback circuit reduces voltages applied to the bitlines or digit lines in order to avoid thresholding the cells. The voltage reduction by the feedback circuit is triggered when the reading of the memory cell pair is complete.

    ARCHITECTURE FOR MULTIDECK MEMORY ARRAYS
    12.
    发明公开
    ARCHITECTURE FOR MULTIDECK MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240237360A1

    公开(公告)日：2024-07-11

    申请号：US18617466

    申请日：2024-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/20

    CPC classification number: H10B63/84 ,  G11C13/0004 ,  G11C13/003 ,  H10N70/231 ,  G11C2213/71

    Abstract: An array of memory cells in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels.

    MEMORY DEVICE TO PRECHARGE BITLINES PRIOR TO SENSING MEMORY CELLS
    13.
    发明公开
    MEMORY DEVICE TO PRECHARGE BITLINES PRIOR TO SENSING MEMORY CELLS 审中-公开

    公开(公告)号：US20240212744A1

    公开(公告)日：2024-06-27

    申请号：US18537685

    申请日：2023-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi

    IPC: G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

    CPC classification number: G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device uses an architecture having a precharge transistor in parallel with a cascode transistor. The precharge transistor (e.g., a p-channel device) performs precharging of a bitline to a fixed constant voltage in preparation for sensing a memory cell. The cascode transistor (e.g., an n-channel device) is used to determine the voltage of the bitline during sensing and discharges a sensing node if the memory cell switches (e.g., snaps). The sensing node is coupled to an input of a detector that determines the logic state of the memory cell.

    COUNTER-BASED METHODS AND SYSTEMS FOR ACCESSING MEMORY CELLS
    15.
    发明申请
    COUNTER-BASED METHODS AND SYSTEMS FOR ACCESSING MEMORY CELLS 有权

    公开(公告)号：US20230110946A1

    公开(公告)日：2023-04-13

    申请号：US17044150

    申请日：2020-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

    IPC: G06F3/06

    Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.

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