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    Cascoded sense amplifiers for self-selecting memory
    1.
    发明授权
    Cascoded sense amplifiers for self-selecting memory 有权

    公开(公告)号：US12300316B2

    公开(公告)日：2025-05-13

    申请号：US17896963

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi ,  Michele Maria Venturini ,  Claudia Palattella

    IPC: G11C13/00

    Abstract: Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.

    TECHNIQUES TO PERFORM A SENSE OPERATION
    3.
    发明公开
    TECHNIQUES TO PERFORM A SENSE OPERATION 审中-公开

    公开(公告)号：US20230206978A1

    公开(公告)日：2023-06-29

    申请号：US17646259

    申请日：2021-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Michele Maria Venturini

    IPC: G11C11/22 ,  G11C7/12 ,  H01L27/11514

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C7/12 ,  H01L27/11514

    Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

    DIFFERENTIAL SUBTHRESHOLD READ OF MEMORY CELL PAIR IN A MEMORY DEVICE
    5.
    发明公开
    DIFFERENTIAL SUBTHRESHOLD READ OF MEMORY CELL PAIR IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230377646A1

    公开(公告)日：2023-11-23

    申请号：US17748666

    申请日：2022-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Umberto di Vincenzo ,  Michele Maria Venturini

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2013/0042 ,  H03K19/20

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a differential read operation is performed on a memory cell pair. Bitlines or digit lines are used to select the memory cells. The read operation is performed in a subthreshold mode in which the memory cells of the pair do not threshold (e.g., do not switch or snap). A voltage on a wordline used to select the memory cell pair is ramped to increasing magnitudes of voltage while the bitline or digit line voltages are held fixed. One or more detectors are used to determine a difference in leakage currents of the two memory cells. A logic state is determined (e.g., using at least one detector) based on the difference in leakage currents. A feedback circuit reduces voltages applied to the bitlines or digit lines in order to avoid thresholding the cells. The voltage reduction by the feedback circuit is triggered when the reading of the memory cell pair is complete.

    Performing sense operations in memory
    6.
    发明授权
    Performing sense operations in memory 有权

    公开(公告)号：US12288592B2

    公开(公告)日：2025-04-29

    申请号：US17873991

    申请日：2022-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

    IPC: G11C29/50

    Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

    Techniques to perform a sense operation
    7.
    发明授权
    Techniques to perform a sense operation 有权

    公开(公告)号：US11798608B2

    公开(公告)日：2023-10-24

    申请号：US17646259

    申请日：2021-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Michele Maria Venturini

    IPC: G11C11/22 ,  G11C7/12 ,  H10B53/20

    CPC classification number: G11C11/2273 ,  G11C7/12 ,  G11C11/221 ,  H10B53/20

    Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

    Sensing component with a common node
    8.
    发明授权
    Sensing component with a common node 有权

    公开(公告)号：US11756602B2

    公开(公告)日：2023-09-12

    申请号：US17646261

    申请日：2021-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Michele Maria Venturini

    IPC: G11C11/22 ,  G11C16/28 ,  G11C16/04

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C16/0483 ,  G11C16/28

    Abstract: Methods, systems, and devices for sensing component with a common node are described. A set of sense circuits of a memory device may include a shared differential amplifier having a first branch for each sense circuit and a shared second branch, as well as a shared common node. A respective latch of each sense amplifier may be initialized to a second logic state, and the common node may undergo a voltage ramp to determine the state stored in the memory cell. If the memory cell stores the first logic state, the sense amplifier may couple with the common node to draw the current and switch the state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state the current may not be drawn and the state of the latch may not switch.

    MEMORY DEVICE TO SENSE MEMORY CELLS WITHOUT BITLINE PRECHARGE
    9.
    发明公开
    MEMORY DEVICE TO SENSE MEMORY CELLS WITHOUT BITLINE PRECHARGE 审中-公开

    公开(公告)号：US20240212750A1

    公开(公告)日：2024-06-27

    申请号：US18536098

    申请日：2023-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Michele Maria Venturini ,  Umberto di Vincenzo

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device controls a power supply to a detector that is used to sense a voltage of a bitline coupled to a memory cell. An output of the detector indicates a logic state of the selected memory cell. By controlling a voltage of the power supply, a detection threshold of the detector can be increased as the voltage on the bitline increases. This permits the detector to be used without requiring precharge of the bitline.

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