公开(公告)号：US20240347102A1

公开(公告)日：2024-10-17

申请号：US18542581

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Ki-Jun Nam ,  Won Joo Yun ,  Shingo Mitsubori

IPC: G11C11/4093

CPC classification number: G11C11/4093

Abstract: Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.

公开(公告)号：US20230051183A1

公开(公告)日：2023-02-16

申请号：US17398863

申请日：2021-08-10

Applicant: Micron Technology, Inc.

Inventor： Won Joo Yun ,  Sang-Hoon Shin

IPC: G06F15/78 ,  G11C7/10

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

公开(公告)号：US20240160600A1

公开(公告)日：2024-05-16

申请号：US18421686

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Won Joo Yun ,  Sang-Hoon Shin

IPC: G06F15/78 ,  G11C7/10

CPC classification number: G06F15/7871 ,  G06F15/7892 ,  G11C7/1057 ,  G11C7/1084

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. A reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

公开(公告)号：US11855812B2

公开(公告)日：2023-12-26

申请号：US17736802

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Won Joo Yun

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

公开(公告)号：US20230362040A1

公开(公告)日：2023-11-09

申请号：US17736802

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Won Joo Yun

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

公开(公告)号：US11677537B2

公开(公告)日：2023-06-13

申请号：US17204681

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun ,  Baekkyu Choi

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H04L7/02

CPC classification number: H04L7/02

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

公开(公告)号：US20230025173A1

公开(公告)日：2023-01-26

申请号：US17385412

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun

IPC: G06F1/10 ,  G06F1/12 ,  G06F1/08

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

公开(公告)号：US20210288843A1

公开(公告)日：2021-09-16

申请号：US16820461

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Won Joo Yun ,  Jennifer E. Taylor

IPC: H04L25/03 ,  H03F3/45 ,  G11C11/4093

Abstract: Continuous time linear equalization devices are disclosed. A continuous time linear equalization device may include a first circuit including a first differential amplification element coupled to a first adjustable source degeneration element. The continuous time linear equalization device may also include a second circuit having an input coupled to an output of the first circuit and including a second differential amplification element coupled to a second adjustable source degeneration element. Systems are also disclosed.