公开(公告)号：US20230350579A1

公开(公告)日：2023-11-02

申请号：US17637428

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liu Yang ,  Xiaolai Zhu ,  Bin Zhao

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

公开(公告)号：US12210448B2

公开(公告)日：2025-01-28

申请号：US18037631

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US20240272832A1

公开(公告)日：2024-08-15

申请号：US18586207

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

公开(公告)号：US20240211168A1

公开(公告)日：2024-06-27

申请号：US18600269

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064

Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

公开(公告)号：US20230376245A1

公开(公告)日：2023-11-23

申请号：US17750131

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

公开(公告)号：US20230195356A1

公开(公告)日：2023-06-22

申请号：US17555160

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604

Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.