公开(公告)号：US20190279892A1

公开(公告)日：2019-09-12

申请号：US16421340

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G01B11/14 ,  G03F9/00 ,  G03F7/20

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US10242901B2

公开(公告)日：2019-03-26

申请号：US16046201

申请日：2018-07-26

Applicant: Micron Technology, Inc.

Inventor： Yang Chao ,  Keith E. Ypma ,  Steve J. Strauch

IPC: H01L21/68 ,  G03F7/20 ,  G03F9/00 ,  G01B11/14

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

公开(公告)号：US20160172242A1

公开(公告)日：2016-06-16

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US09299663B2

公开(公告)日：2016-03-29

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/04 ,  H01L23/544 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20150333014A1

公开(公告)日：2015-11-19

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。