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公开(公告)号:US10170493B1
公开(公告)日:2019-01-01
申请号:US15848398
申请日:2017-12-20
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John Mark Meldrim , Everett A. McTeer
IPC: H01L27/11556 , H01L27/11582 , H01L21/285 , H01L27/11565 , H01L27/11519
Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
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公开(公告)号:US20230389313A1
公开(公告)日:2023-11-30
申请号:US17869586
申请日:2022-07-20
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , Jiewei Chen , John D. Hopkins , Everett A. McTeer
IPC: H01L27/11582 , H01L27/11556
CPC classification number: H01L27/11582 , H01L27/11556
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.
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公开(公告)号:US20230121315A1
公开(公告)日:2023-04-20
申请号:US18083428
申请日:2022-12-16
Applicant: Micron Technology, Inc.
Inventor: David Ross Economy , Rita J. Klein , Jordan D. Greenlee , John Mark Meldrim , Brenda D. Kraus , Everett A. McTeer
Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
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公开(公告)号:US20230016742A1
公开(公告)日:2023-01-19
申请号:US17375602
申请日:2021-07-14
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , Yongjun Jeff Hu , Rita J. Klein , Everett A. McTeer
IPC: H01L29/51 , H01L27/11556 , H01L27/11582 , H01L29/788 , H01L29/792
Abstract: Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoOxNy, where each of “x” and “y” is from 0 to 4.0; and (b): MoMz, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers. The memory cells individually comprise the channel material of individual of the channel-material strings, the storage material, the at least one of AlOq, ZrOq, and HfOq, the at least one of the (a) and the (b), and the metal material. Other embodiments are disclosed.
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公开(公告)号:US11315877B2
公开(公告)日:2022-04-26
申请号:US16817267
申请日:2020-03-12
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John D. Hopkins , Rita J. Klein , Everett A. McTeer , Lifang Xu , Daniel Billingsley , Collin Howder
IPC: H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522
Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号:US20220028996A1
公开(公告)日:2022-01-27
申请号:US17496715
申请日:2021-10-07
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , Rita J. Klein , Everett A. McTeer , John Mark Meldrim
IPC: H01L29/49 , H01L27/11556 , H01L27/11582
Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
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公开(公告)号:US20210066332A1
公开(公告)日:2021-03-04
申请号:US17071980
申请日:2020-10-15
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John Mark Meldrim , Everett A. McTeer
IPC: H01L27/11556 , H01L27/11582 , H01L21/285 , H01L27/11565
Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
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公开(公告)号:US10916564B2
公开(公告)日:2021-02-09
申请号:US16866236
申请日:2020-05-04
Applicant: Micron Technology, Inc.
Inventor: David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L21/311 , H01L27/11565 , H01L21/768 , H01L27/1157
Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号:US20210005732A1
公开(公告)日:2021-01-07
申请号:US16458400
申请日:2019-07-01
Applicant: Micron Technology, Inc.
Inventor: David Ross Economy , Rita J. Klein , Jordan D. Greenlee , John Mark Meldrim , Brenda D. Kraus , Everett A. McTeer
IPC: H01L29/49 , H01L27/11519 , H01L27/11565 , H01L27/11556 , H01L27/11582
Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
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公开(公告)号:US20200266210A1
公开(公告)日:2020-08-20
申请号:US16866236
申请日:2020-05-04
Applicant: Micron Technology, Inc.
Inventor: David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC: H01L27/11582 , H01L27/1157 , H01L21/768 , H01L27/11565 , H01L21/311 , H01L27/11519 , H01L27/11556
Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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